MEMORY SYSTEM

• US 20090222617A1
• Filed: 02/27/2009
• Published: 09/03/2009
• Est. Priority Date: 03/01/2008
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Matsuzaki, Hidenori, Hatsuda, Kosuke, YANO, Junji
• Granted Patent: US 8,706,950 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/22 Employing cache memory using specific memory technology
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 3/0614 Improving the reliability of storage systems
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/88 with partially good memories

Abstract

A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus.

Claims

1. A memory system comprising:

a first storage area functioning as a write cache included in a volatile semiconductor memory from which data can be read out and to which data can be written in a unit equal to or smaller than a sector unit;

a second storage area functioning as a read cache included in a volatile semiconductor memory from which data is read out and to which data is writ equal to or smaller than the sector unit;

a third storage area included in a nonvolatile semiconductor memory from which data is read out and to which data is written in a page unit and in which data is erased in a block unit twice or larger natural number times as large as the page unit; and

a controller that stores, when a data writing request is received from a host apparatus, data transferred from the host apparatus in the first storage area, transfers, when the stored data satisfies a predetermined condition, the data to the third storage area as data in a first management unit having a size natural number times as large as the sector unit, transfers, when the stored data does not satisfy the predetermined condition, the data to the third storage area as data in a second management unit having a size twice or larger natural number times as large as the first management unit, and reads out, when a data readout request is received from the host apparatus, requested data from the third storage area and transfers the data to the host apparatus via the second storage area, wherein

the controller includes a first management table for managing, as a first failure area number, a number of failure areas in the first management unit that occur in the third storage area, and

the controller switches, according to the first failure area number, an operation mode in processing at least one of the data writing request and the data readout request from the host apparatus from a first operation mode to a second operation mode.

2. The memory system according to claim 1, wherein

the controller further includes a second management table for managing, as a second failure area number, a number of failure areas in the block unit that occur in the third storage area, and

the controller switches, according to the second failure area number, an operation mode in processing at least one of the data writing request and the data readout request from the host apparatus from a first operation mode to a second operation mode.

3. The memory system according to claim 2, wherein

the third storage area includes a fourth storage area for performing data management in the first management unit and a fifth area for performing data management in the second management unit, and

the controller selects a plurality of the block units from the third storage area to form a logical block and allocates at least one logical block unit to each of the fourth storage area and the fifth storage area.

4. The memory system according to claim 1, wherein, in the first operation mode, the controller stores data designated by the data writing request from the host apparatus in the first storage area until a predetermined flushing condition is satisfied.

5. The memory system according to claim 4, wherein, in the second mode, the controller stores data designated by the data writing request from the host apparatus in the first storing unit and transfers the data to the third storage area regardless of the predetermined flushing condition.

6. The memory system according to claim 5, wherein

the controller switches, according to the first failure area number, an operation mode in processing at least one of the data writing request and the data readout request from the host apparatus from the second operation mode to the third operation mode, and

in the third operation mode, the controller does not permit the data writing request from the host apparatus and permits the data readout request from the host apparatus.

7. The memory system according to claim 6, wherein the controller switches the operation mode from the first operation mode to the second operation mode when a number of remaining entries in a failure area in the first management unit that can be registered in the first management table decreases to be equal to or smaller than a first threshold.

8. The memory system according to claim 7, wherein the controller switches the operation mode from the second operation mode to the third operation mode when a number of remaining entries in a failure area in the first management unit that can be registered in the first management table decreases to be equal to or smaller than a second threshold.

9. The memory system according to claim 2, wherein, in the first operation mode, the controller stores data designated by the data writing request from the host apparatus in the first storage area until a predetermined flushing condition is satisfied.

10. The memory system according to claim 9, wherein, in the second mode, the controller stores data designated by the data writing request from the host apparatus in the first storing unit and transfers the data to the third storage area regardless of the predetermined flushing condition.

11. The memory system according to claim 10, wherein

the controller switches, according to the second failure area number, an operation mode in processing at least one of the data writing request and the data readout request from the host apparatus from the second operation mode to the third operation mode, and

in the third operation mode, the controller does not permit the data writing request from the host apparatus and permits the data readout request from the host apparatus.

12. The memory system according to claim 11, wherein the controller switches the operation mode from the first operation mode to the second operation mode when a number of remaining entries in a failure area in the first management unit that can be registered in the first management table decreases to be equal to or smaller than a first threshold.

13. The memory system according to claim 12, wherein the controller switches the operation mode from the first operation mode to the second operation mode when a number of remaining entries in a failure area in the first management unit that can be registered in the first management table decreases to be equal to or smaller than a first threshold.

14. The memory system according to claim 11, wherein the controller switches the operation mode from the first operation mode to the second operation mode when a number of remaining entries in a failure area in the block unit that can be registered in the second management table decreases to be equal to or smaller than a third threshold.

15. The memory system according to claim 14, wherein the controller switches the operation mode from the second operation mode to the third operation mode when a number of remaining entries in a failure area in the block unit that can be registered in the second management table decreases to be equal to or smaller than a forth threshold.

16. The memory system according to claim 13, wherein the controller switches the operation mode from the first operation mode to the second operation mode when a number of remaining entries in a failure area in the block unit that can be registered in the second management table decreases to be equal to or smaller than a third threshold.

17. The memory system according to claim 16, wherein the controller switches the operation mode from the second operation mode to the third operation mode when a number of remaining entries in a failure area in the block unit that can be registered in the second management table decreases to be equal to or smaller than a fort threshold.

18. The memory system according to claim 6, wherein the controller switches the operation mode from the second operation mode to the third operation mode when logical blocks that can be allocated to the fourth storage area or the fifth storage area do not remain in the third storage area.

19. The memory system according to claim 11, wherein the controller switches the operation mode from the second operation mode to the third operation mode when logical blocks that can be allocated to the fourth storage area or the fifth storage area do not remain in the third storage area.