Method and Apparatus for Reducing Test Case Generation Time in Processor Testing

• US 20090222647A1
• Filed: 03/03/2008
• Published: 09/03/2009
• Est. Priority Date: 03/03/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Martin-de-Nicolas, Pedro, Feng, Guo H.
• Granted Patent: US 7,836,343 B2
• Time in Patent Office: Days
• US Class Current: 712/227
• CPC Class Codes: G06F 11/263 Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming

Abstract

A method, apparatus and computer program product are provided for use in a system that includes one or more processors, and multiple threads that are respectively associated with the one or more processors. One embodiment of the invention is directed to a method that includes the steps of generating one or more test cases, wherein each test case comprises a specified set of instructions in a specified order, and defining a plurality of thread hardware allocations, each corresponding to a different one of the threads. The thread hardware allocation corresponding to a given thread comprises a set of processor hardware resources that are allocated to the given thread for use in executing test cases. The method further includes executing a particular one of the test cases on a first thread hardware allocation, in order to provide a first set of test data, and thereafter executing the particular test case using a second thread hardware allocation, in order to provide a second set of test data.

Claims

1. In a system including one or more processors and multiple threads that are respectively associated with the one or more processors, a computer implemented method for using test cases in processor testing, wherein said method comprises the steps of:

generating one or more test cases, wherein each test case comprises a specified set of instructions in a specified order;

defining a plurality of thread hardware allocations, corresponding to different ones of said threads, wherein the thread hardware allocation corresponding to a given thread comprises a set of processor hardware resources allocated to said given thread for use in executing test cases; and

executing a particular one of said test cases on a first thread hardware allocation, in order to provide a first set of test data, and thereafter executing said particular test case on a second thread hardware allocation, in order to provide a second set of test data.

2. The method of claim 1, wherein:

a different test case is generated by each of said threads, wherein the test case generated by a given thread is first executed on the thread hardware allocation corresponding to said given thread, and is then shifted to a different hardware thread allocation and executed thereon, wherein each of said executions provides a set of test data associated with operation of said one or more processors.

3. The method of claim 1, wherein:

each thread in a group comprising N of said threads initially generates one of N test cases, and thereafter each of said N threads successively executes a plurality of said N test cases on its thread hardware allocation.

4. The method of claim 3, wherein:

each of said N threads generates a new test case only after executing a specified plurality of said N test cases.

5. The method of claim 3, wherein:

each of said N test cases is executed on the thread hardware allocation corresponding to each of said N threads.

6. The method of claim 3, wherein:

after execution on one thread hardware allocation, one of said N test cases is shifted to another thread hardware allocation for execution, in accordance with a prespecified shift pattern.

7. The method of claim 1, wherein:

a number of said test cases are placed into a pool, and each of said threads randomly selects test cases from said pool for execution on its corresponding thread hardware allocation.

8. The method of claim 1, wherein:

said method includes selectively processing said first and second sets of test data, in order to verify specified characteristics of said one or more processors.

9. The method of claim 8, wherein:

said test data is compared with data representing expected characteristics of said one or more processors.

15. The computer program product of claim 3, wherein:

after execution on one thread hardware allocation, one of said N test cases is shifted to another thread hardware allocation for execution, in accordance with a prespecified shift pattern.

10. In a system including one or more processors and multiple threads that are respectively associated with the one or more processors, a computer program product executed on a computer readable medium for using test cases in processor testing, wherein said computer program product comprises:

instructions for generating one or more test cases, wherein each test case comprises a specified set of instructions in a specified order;

instructions for defining a plurality of thread hardware allocations, corresponding to different ones of said threads, wherein the thread hardware allocation corresponding to a given thread comprises a set of processor hardware resources allocated to said given thread for use in executing test cases; and

instructions for executing a particular one of said test cases on a first thread hardware allocation, in order to provide a first set of test data, and thereafter executing said particular test case on a second thread hardware allocation, in order to provide a second set of test data.

11. The computer program product of claim 10, wherein:

a different test case is generated by each of said threads, wherein the test case generated on a given thread is first executed on the thread hardware allocation corresponding to said given thread, and is then shifted to a different hardware thread allocation and executed thereon, wherein each of said executions provides a set of test data associated with operation of said one or more processors.

12. The computer program product of claim 10, wherein:

each thread in a group comprising N of said threads initially generates one of N test cases, and thereafter each of said N threads successively executes a plurality of said N test cases on its thread hardware allocation.

13. The computer program product of claim 12, wherein:

each of said N threads generates a new test case only after executing a specified plurality of said N test cases.

14. The computer program product of claim 12, wherein:

each of said N test cases is executed on the thread hardware allocation corresponding to each of said N threads.

16. In a system including one or more processors and multiple threads that are respectively associated with the one or more processors, apparatus for using test cases in processor testing, wherein said apparatus comprises:

a component for generating one or more test cases, wherein each test case comprises a specified set of instructions in a specified order;

a component for defining a plurality of thread hardware allocations, corresponding to different ones of said threads, wherein the thread hardware allocation corresponding to a given thread comprises a set of processor hardware resources allocated to said given thread for use in executing test cases; and

a component for executing a particular one of said test cases on a first thread hardware allocation, in order to provide a first set of test data, and thereafter executing said particular test case on a second thread hardware allocation, in order to provide a second set of test data.

17. The apparatus of claim 16, wherein:

a different test case is generated by each of said threads, wherein the test case generated on a given thread is first executed on the thread hardware allocation corresponding to said given thread, and is then shifted to a different hardware thread allocation and executed thereon, wherein each of said executions provides a set of test data associated with operation of said one or more processors.

18. The apparatus of claim 16, wherein:

each thread in a group comprising N of said threads initially generates one of N test cases, and thereafter each of said N threads successively executes a plurality of said N test cases on its thread hardware allocation.

19. The apparatus of claim 18, wherein:

each of said N threads generates a new test case only after executing a specified plurality of said N test cases.

20. The apparatus of claim 16, wherein:

said apparatus includes a comparator for comparing said test data with data representing expected characteristics of said one or more processors.