DECODING SCHEME FOR CORRECTING BOTH ERASURES AND ERRORS OF REED-SOLOMON CODES IN A DIGITAL COMMUNICATION SYSTEM

• US 20090222712A1
• Filed: 03/03/2008
• Published: 09/03/2009
• Est. Priority Date: 03/03/2008
• Status: Abandoned Application

• Current Assignee: Legend Silicon Corporation
• Original Assignee: Legend Silicon Corporation
• Inventors: CHEN, LEI, ZHONG, YAN
• Application Number:
  US12/041,514
• Publication Number:
  US 20090222712A1
• Time in Patent Office: Days
• US Class Current: 714/793
• CPC Class Codes: H03M 13/154 Error and erasure correction, e.g. by using the error and erasure locator or Forney polynomial
• CPC Class Codes: H03M 13/1545 Determination of error locations, e.g. Chien search or other methods or arrangements for the determination of the roots of the error locator polynomial

Abstract

A method for correcting both erasures and errors of Reed-Solomon codes in a digital communication system is provided. The method comprises the steps of: calculating a syndrome; calculating a set of erasure locations; replacing errata evaluator polynomial by a function having a difference value; and replacing errata locator polynomial by a function having the difference value.

Claims

1. A method for correcting both erasures and errors of Reed-Solomon codes in a digital communication system comprising the steps of:

calculating a syndrome;

calculating a set of erasure locations;

replacing errata evaluator polynomial by a function having a difference value; and

replacing errata locator polynomial by a function having the difference value.

2. The method of claim 1 further comprising the step of providing a decoding scheme.

3. The method of claim 1 further comprising the step of finding roots of errata locator polynomial Λ

^(c)(x) by Chien'"'"'s search method.

4. The method of claim 1 further comprising the step of calculating at least one errata magnitude.

5. The method of claim 1 further comprising the step of subtracting an errata vector from a received vector.

6. The method of claim 1 further comprising the step of reducing logic or circuit complexity by multiplying system clock by a factor of n.

7. The method of claim 6 further comprising the step of restoring the system clock speed.

8. The method of claim 6, wherein the factor of n is equal to four.