TEST PROBE CARD SPACE TRANSFORMER

• US 20090223043A1
• Filed: 07/01/2008
• Published: 09/10/2009
• Est. Priority Date: 03/07/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsu, Ming Cheng, Chao, Clinton Chih-Chieh
• Granted Patent: US 8,033,012 B2
• Time in Patent Office: Days
• US Class Current: 29/830
• CPC Class Codes: G01R 1/07378 using an intermediate adapter, e.g. space transformers G01R1/07371 takes precedence
• CPC Class Codes: G01R 3/00 Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments , e.g. of probe tips
• CPC Class Codes: G01R 31/2863 Contacting devices, e.g. sockets, burn-in boards or mounting fixtures in general G01R1/04
• CPC Class Codes: H05K 2201/0367 Metallic bump or raised conductor not used as solder bump solder materials or compositions and methods of application thereof H05K3/3457
• CPC Class Codes: H05K 2201/0376 Flush conductors, i.e. flush with the surface of the printed circuit
• CPC Class Codes: H05K 2201/049 PCB for one component, e.g. for mounting onto mother PCB
• CPC Class Codes: H05K 2203/0542 Continuous temporary metal layer over metal pattern reinforcing the conductive pattern characterised by the electroplating method H05K3/241
• CPC Class Codes: H05K 2203/0574 Stacked resist layers used for different processes
• CPC Class Codes: H05K 3/108 by semi-additive methods; masks therefor characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241
• CPC Class Codes: H05K 3/243 characterised by selective plating, e.g. for finish plating of pads selective plating for making the circuit pattern H05K3/108, H05K3/182
• CPC Class Codes: H05K 3/4007 Surface contacts, e.g. bumps H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3457
• CPC Class Codes: Y10T 29/49004 including measuring or testing of device or component part
• CPC Class Codes: Y10T 29/4902 Electromagnet, transformer or inductor
• CPC Class Codes: Y10T 29/49036 including measuring or testing
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/49128 Assembling formed circuit to base
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49144 by metal fusion
• CPC Class Codes: Y10T 29/49162 by using wire as conductive path
• CPC Class Codes: Y10T 29/49167 with deforming of conductive path
• CPC Class Codes: Y10T 29/49169 : Assembling electrical component directly to terminal or elongated conductor
• CPC Class Codes: Y10T 29/49204 : Contact or terminal manufacturing

Abstract

A space transformer for a semiconductor test probe card and method of fabrication. The method may include depositing a first metal layer as a ground plane on a space transformer substrate having a plurality of first contact test pads defining a first pitch spacing, depositing a first dielectric layer on the ground plane, forming a plurality of second test contacts defining a second pitch spacing different than, the first pitch spacing, and forming a plurality of redistribution leads on the first dielectric layer to electrically couple the first contact test pads to the second contact test pads. In some embodiments, the redistribution leads may be built directly on the space transformer substrate. The method may be used in one embodiment to remanufacture an existing space transformer to produce fine pitch test pads having a pitch spacing smaller than the original test pads. In some embodiments, the test pads may be C4 test pads.

Claims

1. A method for fabricating a semiconductor test probe card space transformer to decrease pitch spacing of a contact test pad, the method comprising:

providing a space transformer having a substrate and plurality of first contact test pads on one side for performing DUT electrical tests, the first test pads defining a first pitch spacing between the test pads;

depositing a first metal layer as a ground plane on the substrate;

depositing a first dielectric layer on the ground plane;

forming a plurality of second test contacts, the second contacts defining a second pitch spacing between the contacts being different than the first pitch spacing; and

forming a plurality of redistribution leads on the first dielectric layer to electrically couple the first contact test pads to the second contact test pads.

2. The method of claim 1, further comprising encapsulating the first contact test pads with a passivation layer.

3. The method of claim 2, wherein the passivation layer is made of a dielectric photoresist material.

4. The method of claim 1, further comprising a step of patterning the first dielectric layer to form recesses for subsequently forming the plurality of redistribution leads and second test contacts.

5. The method of claim 4, wherein the plurality of redistribution leads and second test contacts are formed by depositing a conductive metal in recesses.

6. The method of claim 1, wherein the redistribution leads and second test contacts are formed by depositing a second metal layer on the substrate.

7. The method of claim 1, wherein the second test contacts includes at least one input/out C4 contact isolated from the ground plane and at least one ground contact electrically coupled to the ground plane.

8. A method for remanufacturing a semiconductor test probe card space transformer to decrease pitch spacing of a C4 contact test pad, the method comprising:

providing a space transformer having a substrate and a plurality of first test contacts disposed on a first side of the substrate for performing DUT electrical tests, the first test contacts defining a first pitch spacing between the contacts, the first test contacts including first input/output pads and first ground pads;

depositing a metal ground plane layer on the first side of the substrate;

depositing a first dielectric layer on the ground plane layer;

patterning the first dielectric layer to form recesses therein;

filling at least some of the recesses with a conductive metal to form a plurality of redistribution leads; and

forming a plurality of second test contacts defining a second pitch spacing between the contacts being smaller than the first pitch spacing, at least some of the second test contacts being connected to some of the first test contacts via the redistribution leads.

9. The method of claim 8, further comprising a step of encapsulating the first test contacts with a passivation layer.

10. The method of claim 9, wherein the passivation layer is a photoresist material.

11. The method of claim 8, wherein the first input/output pads are electrically isolated from the ground plane layer.

12. The method of claim 8, wherein the filling step includes simultaneously filling at least some of the recesses with the conductive metal to form conductive bases for the second test contacts.

13. The method of claim 8, further comprising a step of depositing a passivation layer over the first test contacts and redistribution leads.

14. The method of claim 13, further comprising a step of forming recesses in the passivation layer and depositing a conductive metal in the passivation layer recesses for forming the second test contacts.

15. The method of claim 8, wherein the transformer substrate includes a second side opposite the first side and defining conductive channels for a ball grid array.

16. The method of claim 15, further comprising a step of depositing a conductive metal layer on the second side.

17. A method for fabricating a semiconductor test probe card space transformer to decrease pitch spacing of a contact test pad, the method comprising:

providing a space transformer having a substrate and plurality of first contact test pads on one side for performing DUT electrical tests, the first test pads defining a first pitch spacing between the test pads;

forming a plurality of second test contacts on the substrate, the second contacts defining a second pitch spacing between the contacts being different than the first pitch spacing; and

forming a plurality of redistribution leads to electrically couple the first contact test pads to the second contact test pads.

20. The method of claim 17, further comprising forming a ground plane.

18. The method of claim 21, further comprising encapsulating the first and second contact test pads with a passivation layer.

19. The method of claim 22, further comprising forming conductive shafts through the passivation layer to extend the second contact test pads to an exposed surface of the passivation layer for making electrical contact with test card probes for wafer level testing of integrated circuit chips.