Transistor and method of manufacturing the same

• US 20090224238A1
• Filed: 10/23/2008
• Published: 09/10/2009
• Est. Priority Date: 03/07/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Sun-il, Kim, Sang-wook, Song, I-hun, Park, Young-soo, Park, Jae-chul, Kim, Chang-jung
• Granted Patent: US 8,669,551 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A transistor according to example embodiments may include a channel layer, a source and a drain respectively contacting ends of the channel layer, a gate electrode separated from the channel layer, a gate insulating layer interposed between the channel layer and the gate electrode, and/or an insertion layer that is formed between the channel layer and the gate insulating layer. The insertion layer may have a work function different from that of the channel layer.

Claims

1. A transistor comprising:

a channel layer;

a source and a drain respectively contacting opposing ends of the channel layer;

a gate electrode isolated from the channel layer;

a gate insulating layer between the channel layer and the gate electrode; and

an insertion layer between the channel layer and the gate insulating layer, the insertion layer having a work function different from that of the channel layer.

2. The transistor of claim 1, wherein the channel layer includes an oxide.

3. The transistor of claim 2, wherein the oxide is zinc oxide, copper oxide, or nickel oxide.

4. The transistor of claim 1, wherein the channel layer is an n-type semiconductor layer.

5. The transistor of claim 4, wherein the insertion layer is a p-type or an n-type semiconductor layer.

6. The transistor of claim 4, wherein the channel layer is a zinc oxide layer doped with at least one of a group 13 element and a group 14 element.

7. The transistor of claim 4, wherein the insertion layer has a work function greater than that of the channel layer.

8. The transistor of claim 7, wherein the insertion layer has an energy band gap greater than that of the channel layer.

9. The transistor of claim 1, wherein the channel layer is a p-type semiconductor layer.

10. The transistor of claim 9, wherein the insertion layer is an n-type or a p-type semiconductor layer.

11. The transistor of claim 9, wherein the channel layer is one of a copper oxide layer, a nickel oxide layer, and a zinc oxide layer, wherein the nickel oxide layer is optionally doped with a group 4 transition metal and the zinc oxide layer is doped with at least one of a group 1 element, a group 2 element, a group 15 element, and a transition metal.

12. The transistor of claim 9, wherein the insertion layer has a work function smaller than that of the channel layer.

13. The transistor of claim 12, wherein the insertion layer has an energy band gap smaller than that of the channel layer.

14. The transistor of claim 1, wherein the gate electrode is above the channel layer.

15. The transistor of claim 1, wherein the gate electrode is below the channel layer.

16. A method of manufacturing a transistor, comprising:

forming a channel layer and a gate electrode on a substrate, the channel layer isolated from the gate electrode;

forming a source and a drain on the substrate, the source and the drain respectively contacting opposing ends of the channel layer;

forming a gate insulating layer between the channel layer and the gate electrode; and

forming an insertion layer between the channel layer and the gate insulating layer, the insertion layer having a work function different from that of the channel layer.

17. The method of claim 16, wherein the insertion layer is formed to have a work function greater than that of the channel layer.

18. The method of claim 16, wherein the insertion layer is formed to have a work function smaller than that of the channel layer.

19. The method of claim 16, wherein the gate electrode is formed above the channel layer.

20. The method of claim 16, wherein the gate electrode is formed below the channel layer.