Semiconductor device
First Claim
1. A semiconductor device comprising:
- a wiring chip having a pair of first connection pad groups constituted by a plurality of wiring lines arranged in parallel and a plurality of pads connected to respective one end side and other end side of the wiring lines;
a first semiconductor chip, having a group of second connection pads formed of a plurality of pads arranged along one side thereof; and
a second semiconductor chip, having a group of third connection pads formed of a plurality of pads arranged along one side thereof, whereinthe first semiconductor chip and the second semiconductor chip are mounted on the wiring chip such thatthe one side along which the group of second connection pads of the first semiconductor chip are formed and the one side along which the group of third connection pads of the second semiconductor chip are formed to face each other,the group of first connection pads on one side and the group of second connection pads are connected with each other, andthe group of first connection pads on another side and the group of third connection pads are connected with each other.
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Accused Products
Abstract
The present invention provides a semiconductor device which can realize the mounting of a plurality of chips at a high-speed, with high packaging density and at a low cost. In mounting a memory device chip 103 and an ASIC 104 on a wiring chip 102, connection pads 110, 116 are respectively formed along one opposing sides of the memory device chip 103 and the ASIC 104 on the wiring chip 102, the arrangement positions of the respective connection pads 110, 116 define the shortest distance assumes the shortest distance therebetween and, at the same time wiring lines which are formed on the wiring chip 102 are also shortened. Accordingly, it is possible to mount the memory device chip 103 and the ASIC 104 on the wiring chip 102 with high packaging density and, at the same time, since the wiring distance can be shortened, the high speed operation can be realized.
19 Citations
16 Claims
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1. A semiconductor device comprising:
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a wiring chip having a pair of first connection pad groups constituted by a plurality of wiring lines arranged in parallel and a plurality of pads connected to respective one end side and other end side of the wiring lines; a first semiconductor chip, having a group of second connection pads formed of a plurality of pads arranged along one side thereof; and a second semiconductor chip, having a group of third connection pads formed of a plurality of pads arranged along one side thereof, wherein the first semiconductor chip and the second semiconductor chip are mounted on the wiring chip such that the one side along which the group of second connection pads of the first semiconductor chip are formed and the one side along which the group of third connection pads of the second semiconductor chip are formed to face each other, the group of first connection pads on one side and the group of second connection pads are connected with each other, and the group of first connection pads on another side and the group of third connection pads are connected with each other. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A semiconductor device comprising:
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a wiring chip having a pair of first connection pad groups which are constituted of a plurality of wiring lines arranged in parallel and a plurality of pads connected to respective one end side and other end side of the wiring lines and are arranged in a staggered pattern; a first semiconductor chip, having a group of second connection pads which is formed of a plurality of pads arranged along one side thereof in a staggered pattern; and a second semiconductor chip, having a group of third connection pads which is formed of a plurality of pads arranged along one side thereof in a staggered pattern, wherein the first semiconductor chip and the second semiconductor chip are mounted on the wiring chip via bumps by flip chip mounting such that the one side along which the second connection pads of the first semiconductor chip are formed and the one side along which the third connection pads of the second semiconductor chip are formed so as to face each other, the group of first connection pads on one side and the group of second connection pads are connected with each other, the group of first connection pads on another side and the group of third connection pads are connected with each other, and the first semiconductor chip and the second conductor chip are connected with each other by a bus line connection via bus drivers and bus detectors which are provided to the respective chips, a semiconductor substrate which constitutes the wiring chip, a semiconductor substrate which constitutes the first semiconductor chip and a semiconductor substrate which constitutes second semiconductor chip are formed of a silicon substrate, the first semiconductor chip is a memory device chip having a memory means which inputs and outputs signals in parallel for each predetermined number of bits, and the second semiconductor chip is a logic circuit chip which inputs and outputs signals in parallel for each predetermined number of bits with the memory device chip, and the respective pads of the second group of connection pads of the first semiconductor chip and the respective pads of the third group of connection pads of the second semiconductor chip are connected with each other via the wiring lines such that all of the plurality of wiring lines arranged on the wiring chip have the same wiring length, wherein the pads of the second group of connection pads of the first semiconductor chip positioned closest to opposing sides of the first semiconductor chip and the second semiconductor chip and the pads of the third group of connection pads of the second semiconductor chip positioned remotest from the opposing sides are connected and, at the same time, the pads of the second group of the connection pads of the first semiconductor chip positioned remotest from the opposing sides and the pads of the third group of the connection pads of the second semiconductor chip positioned closest to the opposing sides are connected.
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Specification