ISOLATION CIRCUIT

• US 20090224242A1
• Filed: 05/19/2009
• Published: 09/10/2009
• Est. Priority Date: 06/20/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Cowles, Timothy B., Lunde, Aron T.
• Granted Patent: US 7,952,169 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence

Abstract

An isolation circuit, comprising a first transistor having a gate, a first source/drain terminal, and a second source/drain terminal, a first pad coupled to the gate of the first transistor, the first pad operable to receive an enable signal, a second pad coupled to the first source/drain of the first transistor, the second pad operable to receive a ground potential, a first fuse device coupling the second source/drain terminal to a node, a second fuse device coupling the node to the first pad, a third pad operable to receive a signal to be applied to at least one die, and a second transistor operable to selectively transfer the signal received at the third pad to the at least one die in response to a control signal provided by the node.

Claims

1. An isolation circuit, comprising:

a first transistor having a gate, a first source/drain terminal, and a second source/drain terminal;

a first pad coupled to the gate of the first transistor, the first pad operable to receive an enable signal;

a second pad coupled to the first source/drain of the first transistor, the second pad operable to receive a ground potential;

a first fuse device coupling the second source/drain terminal to a node;

a second fuse device coupling the node to the first pad;

a third pad operable to receive a signal to be applied to at least one die; and

a second transistor operable to selectively transfer the signal received at the third pad to the at least one die in response to a control signal provided by the node;

wherein the first transistor, the second transistor, the first pad, the second pad, the first fuse device, and the second fuse device are in a scribe line formed on a wafer including the at least one die.

2. The isolation circuit of claim 1, wherein the isolation circuit is operable to have the first fuse device blown and the second fuse device left intact to transfer the enable signal at the first pad to the node and to the second transistor in order to activate the second transistor to transfer the signal applied to the third pad to the at least one die.

3. The isolation circuit of claim 1, wherein the isolate circuit is operable to have the first fuse device left intact and to have the second fuse device blown to couple the node to the second pad through the first transistor when an enable signal is received at the first pad, and then to further transfer any ground potential at the second pad to the second transistor in order to prevent the second transistor from transferring the signal applied to the third pad to the at least one die.

4. The isolation circuit of claim 1, further including:

a fourth pad in the scribe line, the fourth pad operable to receive a second signal; and

a third transistor in the scribed line coupled to the fourth pad and to the at least one die, the third transistor coupled to the node and operable to selectively couple any received second signal from the fourth pad to the at least one die based on the control signal provided at the node.

5. The isolation circuit of claim 4, wherein the signal received at the third pad is power, and the second signal received at the forth pad is a test signal.

6. The isolation circuit of claim 4, further including:

an anti-fuse logic circuit located in the die and having an output operable to provide an anti-fuse control signal;

a fifth pad located in the die; and

a fourth transistor, the fourth transistor in the die and coupled to the fourth pad to the fifth pad and coupled to the anti-fuse control signal, the anti-fuse control signal operable to control operation of the fourth transistor.

7. The isolation circuit of claim 6, wherein the anti-fuse logic circuit is operable to be blown in order to turn the fourth transistor off and to isolate the fifth pad from the fourth pad.

8. The isolation circuit of claim 1, where at least one of the first fuse device and the second fuse device is formed from a metal.

9. The isolation circuit of claim 1, wherein the scribe line is operable to be removed from the at least one die by sawing.

10. The isolation circuit of claim 1, wherein at least one of the first pad and the second pad is located in a distribution layer.

11. The isolation circuit of claim 1, wherein in each of the first pad, the second pad, and the third pad are located in a redistribution layer.

12. An isolation circuit, comprising:

a first transistor having a gate, a first source/drain terminal, and a second source/drain terminal;

a first pad coupled to the gate of the first transistor, the first pad operable to receive an enable signal;

a second pad coupled to the first source/drain of the first transistor, the second pad operable to receive a ground potential;

a first fuse device coupling the second source/drain terminal to a node;

a second fuse device coupling the node to the first pad;

a third pad operable to receive a first signal; and

a second transistor operable to selectively couple the third pad to at least one die in response to a control signal provided by the node;

wherein the first transistor, the first pad, the second pad, the first fuse device, and the second fuse device are in a scribe line of a wafer, and the second transistor is in a die on the wafer.

13. The isolation circuit of claim 12, wherein the isolation circuit is operable to have the first fuse device blown and the second fuse device left intact to transfer the enable signal at the first pad to the node and to the second transistor in order to activate the second transistor to transfer any first signal applied to the third pad to the at least one die.

14. The isolation circuit of claim 12, wherein the isolate circuit is operable to have the first fuse device left intact and to have the second fuse device blown to couple the node to the second pad through the first transistor when an enable signal is received at the first pad, and then to further transfer any ground potential at the second pad to the second transistor in order to prevent the second transistor from transferring any first signal applied to the third pad to the at least one die.

15. The isolation circuit of claim 12, further including:

a third transistor in the die coupled to a gate of the second transistor and to ground and having a third transistor gate connected a Vcc, the third transistor operable to couple the gate of the second transistor to ground and to turn off the second transistor and prevent any signal provided at the third pad from being transferred to the at least one die.

16. A method of making an isolation circuit comprising:

forming a first pad in a scribe line of a wafer, the first pad operable to receive an enable signal;

forming a second pad in the scribe line of the wafer, the second pad operable to receive a ground potential;

forming a first transistor in the scribe line of the wafer, the first transistor having a gate, a first source/drain terminal and a second source/drain terminal, the gate coupled to the first pad and the first source/drain terminal coupled to the second pad;

forming a first fuse device coupling the second source/drain terminal to a node through the first fuse device;

forming a second fuse device coupling the node to the first pad through the second fuse device;

forming a third pad in the scribe line operable the receive a signal to be applied to a die; and

forming a second transistor couple to the third pad, to the die, and to the node, and operable to selectively couple the signal received at the third pad to the die when the second transistor or is activated by the enable signal provided at the node.

17. The method of claim 16, further including:

blowing the first fuse device and leaving the second fuse device intact;

applying the signal to be applied to the die to the third pad; and

applying the enable signal to the first pad to provide the enable signal to the node and to the second transistor to activate the second transistor to transfer the signal to be applied to the die to the die though the second transistor.

18. The method of claim 16, further including:

blowing the second fuse device and leaving the first fuse device intact;

applying a ground potential to the second pad; and

applying the enable signal to the first pad in order to transfer the ground potential to the node through the first transistor and from the node to the second transistor to prevent any signal to be applied to the die that is provided at the third pad from being transferred to the die.

19. The method of claim 16, wherein forming the second transistor includes forming the second transistor in the scribe line.

20. The method of claim 16, wherein forming the second transistor include forming the second transistor in the die.

21. The method of claim 20, further including:

forming a third transistor in the die coupled to a gate of the second transistor and to ground and having a third transistor gate connected a Vcc; and

applying the Vcc to the third transistor gate to activate the third transistor to couple the gate of the second transistor to ground to turn off the second transistor and prevent any signal to be applied to the die that is provided at the third pad from being transferred to the die.