PATTERNING OF SUBMICRON PILLARS IN A MEMORY ARRAY

• US 20090224244A1
• Filed: 04/10/2009
• Published: 09/10/2009
• Est. Priority Date: 02/17/2005
• Status: Active Grant

• Current Assignee: Woden Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Konevecki, Michael W., Raghuram, Usha
• Granted Patent: US 8,759,176 B2
• Time in Patent Office: Days
• US Class Current: 257/49
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66136 PN junction diodes
• CPC Class Codes: H01L 29/8615 Hi-lo semiconductor devices, e.g. memory devices
• CPC Class Codes: H01L 29/868 PIN diodes
• CPC Class Codes: Y10S 438/947 Subphotolithographic processing

Abstract

Methods in accordance with the invention involve patterning and etching very small dimension pillars, such as in formation of a memory array in accordance with the invention. When dimensions of pillars become very small, the photoresist pillars used to pattern them may not have sufficient mechanical strength to survive the photoresist exposure and development process. Using methods according to the present invention, these photoresist pillars are printed and developed larger than their intended final dimension, such that they have increased mechanical strength, then are shrunk to the desired dimension during a preliminary etch performed before the etch of underlying material begins.

Claims

1. A method for forming a memory array, the method comprising:

forming a layer of etchable material;

forming a layer of photoresist over the etchable material;

patterning and developing the photoresist to form a plurality of photoresist features, each photoresist feature having a largest patterned dimension about equal to a first width, the first width less than about 0.3 micron;

shrinking the photoresist features to a shrunk width, the shrunk width smaller than the first width;

etching etched features in the etchable material; and

forming the memory array comprising a plurality of memory cells, wherein each memory cell comprises one of the etched features.

2. The method of claim 1, wherein the shrunk width is less than about 95 percent of the first width.

3. The method of claim 2, wherein the shrunk width is less than about 90 percent of the first width.

4. The method of claim 1, wherein the shrunk width is at least about 0.01 micron less than the first width.

5. The method of claim 4, wherein the shrunk width is at least about 0.02 micron less than the first width.

6. The method of claim 1, wherein each memory cell comprises a vertically oriented diode.

7. The method of claim 6, wherein each vertically oriented diode comprises one of the etched features.

8. The method of claim 1, further comprising forming a layer of bottom antireflective coating between the layer of etchable material and the layer of photoresist.

9. The method of claim 8, further comprising etching the layer of bottom antireflective coating during the shrinking step.

10. A method for forming a monolithic three dimensional memory array, the method comprising:

a) forming a first memory level by a method comprising;

i) forming a first etchable layer;

ii) forming a photoresist layer over the first etchable layer;

iii) patterning and developing the photoresist layer to form photoresist pillars, each pillar having a first width;

iv) shrinking the photoresist pillars until each pillar has a second width, the second width less than the first width; and

v) etching the first etchable layer to form etched pillars; and

b) monolithically forming a second memory level above the first memory level.

11. The method of claim 10, wherein the first width is the largest patterned dimension of each photoresist pillar.

12. The method of claim 11, wherein the first width is less than about 0.3 micron.

13. The method of claim 12, wherein the second width is less than about 95 percent of the first width.

14. The method of claim 13, wherein the second width is less than about 90 percent of the first width.

15. The method of claim 10, wherein the second width is at least about 0.01 micron less than the first width.

16. The method of claim 15, wherein the second width is at least about 0.02 micron less than the first width.

17. The method of claim 10, wherein the first memory level comprises a first plurality of memory cells, each first memory cell comprising one of the etched pillars.

18. The method of claim 17, wherein each memory cell comprises a diode.

19. The method of claim 18, wherein the monolithic three dimensional memory array is a nonvolatile one-time programmable memory array.

20. The method of claim 10, further comprising forming a layer of bottom antireflective coating between the first etchable layer and the layer of photoresist.

21. The method of claim 20, further comprising etching the layer of bottom antireflective coating during the shrinking step.

22. A monolithic three dimensional memory array comprising:

a) a first memory level formed over a substrate by a method comprising;

i) forming a layer of polycrystalline or amorphous silicon;

ii) depositing photoresist above the polycrystalline or amorphous silicon layer;

iii) patterning and developing the photoresist to form a plurality of photoresist pillars arranged in an evenly spaced grid pattern, the largest patterned dimension of each pillar having a first width;

iv) before substantially etching the layer of polycrystalline or amorphous silicon, reducing the first width to a second width less than the first width; and

v) etching the layer of polycrystalline or amorphous silicon to form etched silicon pillars; and

b) a second memory level monolithically formed on the first level.

23. The monolithic three dimensional memory array of claim 22, wherein the substrate comprises monocrystalline silicon.

24. The monolithic three dimensional memory array of claim 22, wherein the first width is less than about 0.3 micron.

25. The monolithic three dimensional memory array of claim 22, wherein the second width is less than about 95 percent of the first width.

26. The monolithic three dimensional memory array of claim 25, wherein the second width is less than about 90 percent of the first width.

27. The monolithic three dimensional memory array of claim 22, wherein the second width is at least 0.01 micron less than the first width.

28. The monolithic three dimensional memory array of claim 27, wherein the second width is at least 0.02 micron less than the first width.

29. The monolithic three dimensional memory array of claim 22, further comprising at least a third memory level monolithically formed on the second memory level.

30. The monolithic three dimensional memory array of claim 22, wherein the first memory level comprises a first plurality of one-time programmable memory cells.

31. The monolithic three dimensional memory array of claim 30, wherein each of the first plurality of memory cells comprises a diode, the diode comprising amorphous or polycrystalline silicon.

32. The monolithic three dimensional memory array of claim 22, further comprising forming a layer of bottom antireflective coating between the layer of polycrystalline or amorphous silicon and the layer of photoresist.

33. The method of claim 32, further comprising etching the layer of bottom antireflective coating during the reducing step.