Two-way Halo Implant

• US 20090224290A1
• Filed: 03/03/2009
• Published: 09/10/2009
• Est. Priority Date: 03/06/2008
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Miyashita, Katsura
• Application Number:
  US12/396,855
• Publication Number:
  US 20090224290A1
• Time in Patent Office: Days
• US Class Current: 257/272
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A system and method for ion implantation during semiconductor fabrication. An integrated circuit may be designed with proximately located one-directional transistor gates. A two-way halo ion implantation is performed perpendicularly to the transistor gates in order to embed the dopant into the silicon body on the surface of the semiconductor wafer. The two-way halo both reduces the channeling effect by allowing ion implantation beneath the transistor gate, and reduces the halo shadowing effect resulting from halo implanting which is done parallel to the transistor gates.

Claims

1. A semiconductor device comprising:

a silicon layer; and

a first field-effect transistor, including;

a transistor gate disposed on the silicon layer,

a pair of source/drain regions, and

a channel region in the silicon layer,

wherein the silicon layer is doped with ions, such that a portion of the channel region is implanted with a same non-zero concentration of a particular type of ion as a portion of the silicon layer adjacent to the channel region.

2. The semiconductor device of claim 1, wherein the silicon layer is doped with ions at an angle based on the height of a second field-effect transistor adjacent to the first field-effect transistor.

3. The semiconductor device of claim 1, wherein the silicon layer is disposed on an oxide layer.

4. The semiconductor device of claim 1, further comprising two opposing sidewalls formed along the transistor gate, such that one sidewall is on each side of a long axis of said transistor gate, each sidewall having a sidewall spacer disposed on the silicon layer and on the sidewall, wherein a first portion of the silicon layer beneath a sidewall spacer is implanted with a same non-zero concentration of a particular type of ion as a second portion of the silicon layer, said second portion not beneath either the transistor gate or the sidewall, wherein said first portion and said second portion are adjacent.

5. The semiconductor device of claim 1, wherein the concentration of a particular type of ion is a concentration of boron ions.

6. The semiconductor device of claim 1, further comprising:

a static random access memory (SRAM) comprising a plurality of field-effect transistors, said plurality of transistors including said first field-effect transistor.

7. A method for manufacturing a semiconductor device, comprising:

forming a conductive layer on a top surface of a silicon layer, the conductive layer having a width and a length, wherein the length of the conductive layer extends along an axis and is longer than the respective width;

forming a layer of resist on said conductive layer;

directing a first ion stream toward the silicon layer at a first angle not normal to the top surface of the silicon layer, said first angle being perpendicular to the axis;

directing a second ion stream toward the silicon layer at a second angle not normal to the top surface of the silicon layer, said second angle being perpendicular to the axis, wherein said second ion stream originates from an opposite side of the axis from which the first ion stream originates; and

removing at least some of said layer of resist from said conductive layer, wherein only two ion streams are directed toward the silicon layer between steps of forming said layer of resist and removing at least of the said layer of resist.

8. The method of claim 7, wherein the top surface of the silicon layer is not doped by an ion stream directed at an angle parallel to the axis.

9. The method of claim 7, wherein the first and second ion streams are each boron ion streams.

10. The method of claim 7, wherein the conductive layer comprises a plurality of regions of polysilicon.

11. The method of claim 10, further comprising:

forming an SRAM comprising a plurality of transistor gates, wherein said plurality of regions of polysilicon comprise said transistor gates of said SRAM.

12. The method of claim 11, wherein said first ion stream and said second ion stream are directed toward the silicon layer at an angle based on the height one or more of the plurality of transistor gates and a distance between two or more of the plurality of transistor gates.

13. A semiconductor device comprising:

a silicon layer; and

a polysilicon layer disposed on the silicon layer, the polysilicon layer being divided into a plurality of distinct polysilicon regions,

wherein, for each polysilicon region, a first region of the silicon layer underlying the polysilicon region has a same non-zero concentration of a particular type of ion as a second region of the silicon layer not underlying the polysilicon region and immediately adjacent the first region.

14. The semiconductor device of claim 13, wherein each of the polysilicon regions has a width and a length, the length being longer than the width, and has opposing sidewalls extending along the length, further comprising a plurality of sidewall spacers, each sidewall spacer disposed on the silicon layer and on one of the opposing sidewalls of one of the polysilicon regions, wherein for each of the polysilicon regions the second region underlies one of the sidewall spacers.

15. The semiconductor device of claim 13, wherein the concentration of a particular type of ion is a concentration of boron ions.

16. The semiconductor device of claim 13, further comprising:

a static random access memory (SRAM) comprising a plurality of field-effect transistors, said plurality of transistors comprising said plurality of distinct polysilicon regions.