Semiconductor Package with Stacked Semiconductor Die each Having IPD and Method of Reducing Mutual Inductive Coupling by Providing Selectable Vertical and Lateral Separation Between IPD

• US 20090224361A1
• Filed: 03/05/2008
• Published: 09/10/2009
• Est. Priority Date: 03/05/2008
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac Limited
• Inventors: Liu, Kai, Frye, Robert C.
• Granted Patent: US 7,892,858 B2
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06575 Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor package has first and second semiconductor die mounted to a substrate. The first semiconductor die includes a first inductor coil electrically coupled to the substrate. The second semiconductor die is mounted over the first semiconductor die. The second semiconductor die includes a second inductor coil electrically coupled to the substrate. A center of the second inductor coil has a vertical and lateral separation with respect to a center of the first inductor coil which are each selectable to minimize mutual inductive coupling between the first and second inductor coils. A spacer is disposed between the first and second semiconductor die to adjust the vertical separation. The center of the second inductor is positioned laterally within the second semiconductor die with respect to the center of the first inductor to adjust the lateral separation. The mutual inductive coupling decreases with increasing vertical and lateral separation.

Claims

1. A method of making a semiconductor package, comprising:

providing a substrate;

mounting a first semiconductor die to the substrate, the first semiconductor die including a first integrated passive device electrically coupled to the substrate; and

mounting a second semiconductor die over the first semiconductor die, the second semiconductor die including a second integrated passive device electrically coupled to the substrate, wherein a center of the second integrated passive device has a vertical and lateral separation with respect to a center of the first integrated passive device which are each selectable to minimize mutual inductive coupling between the first and second integrated passive devices.

2. The method of claim 1, further including disposing a spacer between the first and second semiconductor die to adjust the vertical separation.

3. The method of claim 1, wherein the vertical separation is selectable from 250-800 micrometers.

4. The method of claim 1, wherein the center of the second integrated passive device is positioned laterally within the second semiconductor die with respect to the center of the first integrated passive device to adjust the lateral separation.

5. The method of claim 1, wherein the lateral separation is selectable from 0-750 micrometers.

6. The method of claim 1, wherein the first and second integrated passive devices each include an inductor coil.

7. The method of claim 1, wherein the mutual inductive coupling decreases with increasing vertical and lateral separation.

8. A method of making a semiconductor package, comprising:

providing a substrate;

mounting a first semiconductor die to the substrate, the first semiconductor die including a first inductor coil electrically coupled to the substrate; and

mounting a second semiconductor die over the first semiconductor die, the second semiconductor die including a second inductor coil electrically coupled to the substrate, wherein a center of the second inductor coil has a vertical or lateral separation with respect to a center of the first inductor coil which is selectable to minimize mutual inductive coupling between the first and second inductor coils.

9. The method of claim 8, further including disposing a spacer between the first and second semiconductor die to adjust the vertical separation.

10. The method of claim 8, wherein the vertical separation is selectable from 250-800 micrometers.

11. The method of claim 8, wherein the center of the second inductor coil is positioned laterally within the second semiconductor die with respect to the center of the first inductor coil to adjust the lateral separation.

12. The method of claim 8, wherein the lateral separation is selectable from 0-750 micrometers.

13. The method of claim 8, wherein the mutual inductive coupling decreases with increasing vertical and lateral separation.

14. A method of making a semiconductor package, comprising:

providing a substrate;

mounting a first semiconductor die to the substrate, the first semiconductor die including a first inductor coil electrically coupled to the substrate; and

mounting a second semiconductor die over the first semiconductor die, the second semiconductor die including a second inductor coil electrically coupled to the substrate, wherein the second inductor coil has a vertical and lateral separation with respect to the first inductor coil which are each selectable to minimize mutual inductive coupling between the first and second inductor coils.

15. The method of claim 14, further including disposing a spacer between the first and second semiconductor die to adjust the vertical separation.

16. The method of claim 14, wherein the vertical separation is selectable from 250-800 micrometers.

17. The method of claim 14, wherein a center of the second inductor is positioned laterally within the second semiconductor die with respect to a center of the first inductor to adjust the lateral separation.

18. The method of claim 14, wherein the lateral separation is selectable from 0-750 micrometers.

19. The method of claim 14, wherein the mutual inductive coupling decreases with increasing vertical and lateral separation.

20. A semiconductor device, comprising:

a substrate;

a first semiconductor die mounted to the substrate, the first semiconductor die including a first inductor coil electrically coupled to the substrate; and

a second semiconductor die mounted over the first semiconductor die, the second semiconductor die including a second inductor coil electrically coupled to the substrate, wherein a center of the second inductor coil has a vertical and lateral separation with respect to a center of the first inductor coil which are each selectable to minimize mutual inductive coupling between the first and second inductor coils.

21. The semiconductor device of claim 20, further including a spacer disposed between the first and second semiconductor die to adjust the vertical separation.

22. The semiconductor device of claim 20, wherein the vertical separation is selectable from 250-800 micrometers.

23. The semiconductor device of claim 20, wherein the center of the second inductor is positioned laterally within the second semiconductor die with respect to the center of the first inductor to adjust the lateral separation.

24. The semiconductor device of claim 20, wherein the lateral separation is selectable from 0-750 micrometers.

25. The semiconductor device of claim 20, wherein the mutual inductive coupling decreases with increasing vertical and lateral separation.