SEMICONDUCTOR CIRCUIT AND METHOD OF FABRICATING THE SAME

• US 20090224364A1
• Filed: 03/03/2009
• Published: 09/10/2009
• Est. Priority Date: 06/24/2003
• Status: Active Grant

• Current Assignee: BeSang Inc.
• Original Assignee: BeSang Inc.
• Inventors: Oh, ChoonSik, Lee, Sang-Yun
• Granted Patent: US 7,863,748 B2
• Time in Patent Office: Days
• US Class Current: 257/532
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01032 Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/0104 Zirconium [Zr]
• CPC Class Codes: H01L 2924/01042 Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/0105 Tin [Sn]
• CPC Class Codes: H01L 2924/01073 Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A bonded semiconductor structure includes a support substrate which carries a first electronic circuit, and an interconnect region carried by the support substrate. The interconnect region includes a capacitor and conductive line in communication with the first electronic circuit. The circuit includes a bonding layer carried by the interconnect region, and a bonded substrate coupled to the interconnect region through the bonding layer.

Claims

1. A bonded semiconductor structure, comprising:

a support substrate which carries a first electronic circuit;

an interconnect region carried by the support substrate, the interconnect region including a capacitor and conductive line in communication with the first electronic circuit;

a bonding layer carried by the interconnect region; and

a bonded substrate coupled to the interconnect region through the bonding layer.

2. The structure of claim 1, further including a bonding interface, wherein the bonded substrate and interconnect region are coupled together through the bonding interface.

3. The structure of claim 2, wherein the bonding interface is between the capacitor and bonded substrate.

4. The structure of claim 1, wherein the bonding layer is between the capacitor and bonded substrate.

5. The structure of claim 1, further including a dielectric material region positioned between the conductive line and bonding layer.

6. The structure of claim 1, further including a dielectric material region positioned between the conductive line and a sidewall of the bonded substrate.

7. The structure of claim 1, wherein the bonded substrate includes a semiconductor material region positioned between the second electronic circuit and bonding layer.

8. The structure of claim 1, wherein the bonded substrate includes a semiconductor material region positioned between the second electronic circuit and bonding interface.

9. The structure of claim 1, further including a second electronic circuit carried by the bonded substrate.

10. The structure of claim 9, wherein the first and second electronic circuits are in communication with each other through the conductive line.

11. The structure of claim 9, further including a second interconnect region carried by the bonded substrate, the second interconnect region being in communication with the second electronic circuit and the conductive line.

12. The structure of claim 9, wherein the bonding layer and second electronic circuit are positioned proximate to a bonding surface and detach layer surface of the bonded substrate, respectively.

13. A bonded semiconductor structure, comprising:

an interconnect region which includes a capacitor and conductive line;

a bonding layer carried by the interconnect region; and

a bonded substrate coupled to the interconnect region through the bonding layer;

wherein the interconnect region includes a first dielectric material region between the bonding layer and capacitor.

14. The structure of claim 13, wherein the bonded substrate includes a detach layer surface positioned away from the bonding layer.

15. The structure of claim 13, further including a second dielectric material region between the bonding layer and conductive line.

16. The structure of claim 13, further including a second dielectric material region between a sidewall of the bonded substrate and the conductive line.

17. The structure of claim 13, further including a support substrate which carries a first electronic circuit, the first electronic circuit being in communication with the capacitor and conductive line.

18. The structure of claim 17, further including a second electronic circuit carried by the bonded substrate, the second electronic circuit being in communication with the first electronic circuit through the conductive line.

19. A method of forming a bonded semiconductor structure, comprising:

providing a support substrate which carries a first electronic circuit;

providing an interconnect region carried by the support substrate, the interconnect region including a capacitor and conductive line in communication with the first electronic circuit;

providing a bonding layer carried by the interconnect region; and

coupling a bonded substrate to the interconnect region through the bonding layer.

20. The method of claim 19, wherein the step of coupling includes forming a bonding interface.

21. The method of claim 19, wherein the step of coupling includes forming a metal-semiconductor bonding interface.

22. The method of claim 19, further including decoupling the bonded substrate from a carrier substrate.

23. The method of claim 19, further including forming a second electronic circuit proximate to a detach layer surface of the bonded substrate.

24. The method of claim 23, further including providing a second interconnect region which provides communication between the second electronic circuit and conductive line.