LOW POWER SUPPLY MAINTAINING CIRCUIT

• US 20090224741A1
• Filed: 03/07/2008
• Published: 09/10/2009
• Est. Priority Date: 03/07/2008
• Status: Abandoned Application

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: McCarthy, Evan, Marholev, Bojko
• Application Number:
  US12/044,726
• Publication Number:
  US 20090224741A1
• Time in Patent Office: Days
• US Class Current: 323/283
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence

Abstract

A circuit may include a load that is configured to enter a low power mode, a capacitor that is operably coupled to the load and that is configured to provide a minimum voltage and current for the load to maintain its state while in the low power mode, a finite state machine that is configured to receive a clock signal and to duty cycle on a periodic basis based on the clock signal and to enable a power-up signal on the periodic basis, and a low-dropout voltage regulator that is operably coupled to the finite state machine and to the capacitor and that is configured to receive the power-up signal from the finite state machine, to power on in response to receiving the power-up signal, to provide a voltage upon power on to the capacitor, and to regulate the voltage to charge the capacitor.

Claims

1. A circuit comprising:

a load that is arranged and configured to enter a low power mode;

a capacitor that is operably coupled to the load and that is arranged and configured to provide a minimum voltage and current for the load to maintain its state while in the low power mode;

a finite state machine that is arranged and configured to receive a clock signal and to duty cycle on a periodic basis based on the clock signal and to enable a power-up signal on the periodic basis; and

a low-dropout voltage regulator that is operably coupled to the finite state machine and to the capacitor and that is arranged and configured to;

receive the power-up signal from the finite state machine,

power on in response to receiving the power-up signal,

provide a voltage upon power on to the capacitor, and

regulate the voltage to charge the capacitor.

2. The circuit of claim 1 wherein the load includes digital circuitry.

3. The circuit of claim 1 wherein the load includes a memory module.

4. The circuit of claim 1 wherein the load includes a counter.

5. The circuit of claim 1 wherein the capacitor is a load capacitance of the load.

6. The circuit of claim 1 wherein the finite state machine is arranged and configured to duty cycle on a configurable periodic basis based on the clock signal and to generate the power-up signal on the periodic basis.

7. The circuit of claim 1 further comprising:

a switch that is operably coupled to the low-dropout voltage regulator and the capacitor and that is arranged and configured to close when the low-dropout voltage regulator is powered on and to open when the low-dropout voltage regulator is powered off.

8. A circuit comprising:

a load that is arranged and configured to enter a low power mode;

a capacitor that is operably coupled to the load and that is arranged and configured to provide a minimum voltage and current for the load to maintain its state while in the low power mode;

a sensor module that is operably coupled to the capacitor and that is arranged and configured to;

sense when a voltage in the capacitor is low and to enable a power-up signal, and

sense when the voltage in the capacitor in charged and to disable the power-up signal; and

a low-dropout voltage regulator that is operably coupled to the sensor module and to the capacitor and that is arranged and configured to;

receive the power-up signal from the sensor module,

power on in response to receiving the power-up signal,

provide a voltage upon power on to the capacitor, and

regulate the voltage to a desired level to charge the capacitor.

9. The circuit of claim 8 wherein the load includes digital circuitry.

10. The circuit of claim 8 wherein the load includes a memory module.

11. The circuit of claim 8 wherein the load includes a counter.

12. The circuit of claim 8 wherein the capacitor is a load capacitance of the load.

13. The circuit of claim 8 further comprising:

a switch that is operably coupled to the low-dropout voltage regulator and the capacitor and that is arranged and configured to close when the low-dropout voltage regulator is powered on and to open when the low-dropout voltage regulator is powered off.

14. A circuit comprising:

a load that is arranged and configured to enter a low power mode;

a first capacitor that is operably coupled to the load and that is arranged and configured to provide a minimum voltage and current for the load to maintain its state while in the low power mode;

a band gap reference module that is arranged and configured to receive a clock signal and to provide a low voltage reference and a high voltage reference;

a first comparator that is operably coupled to the band gap reference module and to the first capacitor and that is arranged and configured to sense a voltage of the first capacitor and to turn on when the voltage of the first capacitor reaches the low voltage reference;

a second comparator that is operably coupled to the band gap reference module and to the first capacitor and that is arranged and configured to sense the voltage of the first capacitor and to turn on when the voltage of the first capacitor reaches the high voltage reference;

a flip-flop, wherein;

a reset input of the flip-flop is operably coupled to an output of the first comparator, and

a clock input of the flip-flop is operably coupled to the second comparator, and

a field effect transistor (FET) that is operably coupled to the flip-flop and to the first capacitor and that is arranged and configured to charge the first capacitor when the first comparator is turned on and to stop charging the first capacitor when the second comparator is turned on.

15. The circuit of claim 14 wherein the load includes digital circuitry.

16. The circuit of claim 14 wherein the first capacitor is a load capacitance of the load.

17. The circuit of claim 14 wherein the FET is a positive channel field effect transistor (pFET).

18. The circuit of claim 14 further comprising:

a resistor that is operably coupled to the FET and that is arranged and configured to reduce noise in the circuit and to limit a speed at which the FET provides a charge to the capacitor.

19. The circuit of claim 14 further comprising:

a second capacitor that is operably coupled to the band gap reference module and to the first comparator and that is arranged and configured to store a charge associated with the low voltage reference; and

a third capacitor that is operably coupled to the band gap reference module and to the second comparator and that is arranged and configured to store a charge associated with the high voltage reference.

20. The circuit of claim 14 wherein only one of the first comparator and the second comparator is on at a same time.