DEVICES AND METHODS FOR DRIVING A SIGNAL OFF AN INTEGRATED CIRCUIT

• US 20090224802A1
• Filed: 03/06/2008
• Published: 09/10/2009
• Est. Priority Date: 03/06/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Keeth, Brent, Hollis, Timothy
• Granted Patent: US 7,733,118 B2
• Time in Patent Office: Days
• US Class Current: 326/82
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2924/15174 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H03K 19/018528 with at least one differential stage

Abstract

Embodiments of the present invention provide electronic devices, memory devices and methods of driving an on-chip signal off a chip. In one such embodiment, an on-chip signal and a second signal complementary to the on-chip signal are generated and provided to the two inputs of a differential driver. One output of the differential driver circuitry is coupled to an externally-accessible output terminal of the package. The other output may be terminated off the chip, but within the package. By routing the output signal and a second complementary output through the package, crosstalk potentially caused by the output signal can be reduced. Simultaneous switching output noise may also be reduced through use of a current-steering differential driver topology. Signal symmetry may also improve, reducing inter-symbol interference.

Claims

1. An electronic device including a package, the electronic device comprising:

at least one externally-accessible terminal configured to couple to a channel; and

an integrated circuit chip, the integrated circuit chip including;

driver circuitry operable to receive an on-chip signal and drive the on-chip signal off of the chip, the driver circuitry having first and second input terminals and first and second output terminals, one of the first and second input terminals coupled to receive the on-chip signal and the other of the first and second input terminals coupled to receive the complement of the on-chip signal, the driver circuitry operable to produce an output signal at the first output terminal and a complement of the output signal at the second output terminal;

a first electrical connector coupled between one of the first or second output terminals and the at least one externally-accessible terminal;

a termination circuit, the termination having an input terminal adjacent to the externally-accessible terminal, the termination operable to terminate a received signal and having an impedance value related to capacitance of the channel; and

a second electrical connector, not coupled to any of the externally-accessible terminals, coupled between the other of the first or second output terminals and the input terminal of the termination circuit.

2. The electronic device of claim 1 wherein the termination circuit and the externally-accessible terminal are located at an edge of the package.

3. The electronic device of claim 1 wherein the second electrical connector is located sufficiently near the first electrical connector to reduce crosstalk caused by the first electrical connector.

4. The electronic device of claim 1 wherein the first and second electrical connectors are of substantially the same length.

5. An electronic device according to claim 1 wherein the first and second electrical connectors include wire bonds.

6. An electronic device according to claim 1 wherein the first and second electrical connectors include conductive traces on a package substrate.

7. An electronic device according to claim 1 wherein the termination includes a capacitance and a resistance comprising a capacitance chosen to simulate a capacitance exhibited by a channel to which the at least one externally-accessible terminal is coupled.

8. An electronic device according to claim 1 further comprising signal generating circuitry operable to generate the on-chip signal and wherein the signal generating circuitry and the driver circuitry are disposed on a common semiconductor substrate.

9. An electronic device according to claim 8 wherein the signal generating circuitry includes a memory cell.

10. An electronic device according to claim 8 wherein the on-chip signal includes a data signal.

11. An electronic device according to claim 8 wherein the on-chip signal includes a clock signal.

12. An electronic device according to claim 1 wherein the driver circuitry includes a first transistor, a second transistor, and current source circuitry, the first and second input terminals of the driver circuitry including gates of the first and second transistors, respectively, and the first and second transistors each including a respective terminal coupled to the current source circuitry.

13. An electronic device including a package, the electronic conprising:

at least one externally-accessible terminal; and

an integrated circuit chip, the integrated circuit chip including;

driver circuitry operable to receive an on-chip signal and drive the on-chip signal off of the chip, the driver circuitry having first and second input terminals and first and second output terminals, one of the first and second input terminals coupled to receive the on-chip signal and the other of the first and second input terminals coupled to receive the complement of the on-chip signal, the driver circuitry operable to produce an output signal at the first output terminal and a complement of the output signal at the second output terminal;

a first electrical connector coupled between one of the first or second output terminals and the at least one externally-accessible terminal;

a termination circuit, the termination circuit operable to terminate a received signal, the termination circuit not coupled to any of the externally-accessible terminals;

a second electrical connector having a length greater than or equal to at least half the length of the first electrical connector coupled between the other of the first or second output terminals and the termination circuit.

14. An electronic device according to claim 13 wherein the length of the second electrical connector is greater than or equal to at least three-quarters of the length of the first electrical connector.

15. An electronic device according to claim 13 wherein the integrated circuit chip further includes additional circuitry coupled between a supply voltage and the driver circuitry to present a resistive load to the driver circuitry.

16. The electronic device of claim 15 wherein the additional circuitry includes an adjustable transistor to select a resistance of the additional circuitry to simulate resistance of a channel to which the at least one externally-accessible terminal is coupleable.

17. The electronic device of claim 13 further comprising signal generating circuitry operable to generate the on-chip signal and wherein the signal generating circuitry includes a memory cell.

18. The electronic device of claim 13 wherein the termination circuit selected to reduce signal reflection in the second electrical connector.

19. A memory device comprising:

a package having at least one externally-accessible terminal configured to coupled to a channel;

an array of memory cells on a substrate within the package;

a command decoder operable to receive a command signal and execute the command;

an address decoder operable to receive an address request from the command decoder and select a cell within the array of memory cells corresponding to the requested address;

an output buffer on the substrate coupled to receive a signal from at least one of the cells in the array of memory cells, the output buffer operable to receive a data signal from the at least one cell and drive the data signal off the substrate, the output buffer comprising;

first and second input terminals and first and second output terminals, one of the first and second input terminals coupled to receive the data signal and the other of the first and second input terminals coupled to receive the complement of the data signal, the output buffer operable to produce an output signal at the first output terminal and a complement of the output signal at the second output terminal;

a first electrical connector coupled between one of the first or second output terminals and the at least one externally-accessible terminal;

a termination circuit inside the package, the termination circuit having an input terminal adjacent to the externally-accessible terminal, but not coupled to any of the externally-accessible terminals, the termination circuit operable to terminate a received signal and having an impedance value related to an impedance of the channel; and

a second electrical connector coupled between the other of the first or second output terminals and the input terminal of the termination circuit.

20. The memory device of claim 19 wherein the first and second electrical connectors are routed through the package substantially alongside one another.

21. (canceled)

22. A method of driving an on-chip signal coupled to an externally-accessible terminal, the method comprising:

receiving an on-chip signal;

generating a second signal complementary to the on-chip signal;

inputting the on-chip signal and the second complementary signal to a differential amplifier; and

generating, with the differential amplifier, a first output signal and a second output signal complementary to the first output signal, wherein;

the first output signal is coupled to the externally-accessible terminal off of the chip; and

wherein

the second output signal is coupled to a termination adjacent the externally-accessible terminal and not coupled to an externally-accessible terminal.

23. The method according to claim 22 wherein the first output signal is coupled through a first electrical connector and the second output signal is coupled through a second electrical connector sufficiently close to the first electrical connector to reduce cross-talk from the first electrical connector.

24. The method according to claim 22 wherein the act of generating the second complementary signal includes generating the second signal having opposite polarity to the on-chip signal.

25. The method according to claim 22 further comprising drawing a substantially constant current through the differential amplifier.