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Preventing a False Lock in a Phase Lock Loop

  • US 20090224837A1
  • Filed: 05/15/2009
  • Published: 09/10/2009
  • Est. Priority Date: 11/01/2004
  • Status: Active Grant
First Claim
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1. A method for preventing a false lock, comprising:

  • receiving a return signal from a stimulated circuit, wherein the return signal is based on an energizing signal;

    processing the return signal;

    mixing the processed return signal with a reference signal;

    determining a phase slope of a resulting baseband signal; and

    if the phase slope does not satisfy a predetermined criteria, then preventing a phase lock loop (PLL) from locking.

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