Cyclic pipeline analog-to-digital converter

• US 20090224951A1
• Filed: 03/10/2008
• Published: 09/10/2009
• Est. Priority Date: 03/10/2008
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Dura, Renaud
• Granted Patent: US 7,652,612 B2
• Time in Patent Office: Days
• US Class Current: 341/110
• CPC Class Codes: H03M 1/14 Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
• CPC Class Codes: H03M 1/144 the steps being performed sequentially in a single stage, i.e. recirculation type H03M1/141, H03M1/143, H03M1/16 take precedence

Abstract

Some embodiments include apparatus and methods having a first module with a capacitor network configured to receive a sample of an analog input signal and an amplifier configured to couple to the capacitor network in a plurality of arrangements to successively generate a plurality of residue signals at an amplifier output node of the amplifier without resetting the amplifier between generation of least two of the plurality of residue signals, and a second module configured to generate a digital signal based on a plurality of intermediate codes generated from the sample signal and the plurality of residue signals, the digital signal including a digital value of the sample.

Claims

1. An apparatus comprising:

a first module including a capacitor network configured to receive a sample of an analog input signal, and an amplifier configured to couple to the capacitor network in a plurality of arrangements to successively generate a plurality of residue signals at an amplifier output node of the amplifier without resetting the amplifier between generation of least two of the plurality of residue signals, the amplifier including a first amplifier input node, a second amplifier input node, and an amplifier output node, the capacitor network including;

a first capacitor configured to couple to the first amplifier input node via a first path, to couple to the second amplifier input node via a second path, to couple to the amplifier output node via at least one of a third path and a fourth path, to couple to a selected one of a first reference node and a second reference node via a fifth path, and to couple to an input node via a sixth path; and

a second capacitor configured to couple to the first amplifier input node via the first path, to couple to the second amplifier input node via the second path, to couple to the amplifier output node via at least one of a seventh path and an eighth path, to couple to the selected one of the first reference node and the second reference node via a ninth path, and to couple to the input node via a tenth path; and

a second module configured to generate a digital signal based on a plurality of intermediate codes generated from the sample and the plurality of residue signals, the digital signal including a digital value of the sample.

2. The apparatus of claim 1, wherein the first and second capacitors form a first pair of capacitors of the capacitor network, the capacitor network includes a second pair of capacitors, and the first pair of capacitors and the second pair of capacitors are configured to selectively receive the sample.

7. The apparatus of claim 1, wherein the first module includes:

a sub analog-to-digital unit configured to generate the plurality of intermediate codes based on the sample and the plurality of residue signals; and

a sub digital-to-analog unit configured to receive the plurality of intermediate codes and provide a signal to the first module during generation of the plurality of residue signals.

8. The apparatus of claim 1, wherein the analog input signal includes a differential signal.

3. An apparatus comprising:

a first module including a capacitor network configured to receive a sample of an analog input signal, and an amplifier configured to couple to the capacitor network in a plurality of arrangements to successively generate a plurality of residue signals at an amplifier output node of the amplifier without resetting the amplifier between generation of least two of the plurality of residue signals; and

a second module configured to generate a digital signal based on a plurality of intermediate codes generated from the sample and the plurality of residue signals, the digital signal including a digital value of the sample, wherein the capacitor network includes a first capacitor and a second capacitor configured to alternately form a feedback path and a reference path of first and second arrangements of the plurality of arrangements to generate a first residue signal and a second residue signal of the plurality of residue signals, the feedback path including a path between the amplifier output node and an amplifier input node of the amplifier, and the reference path including a path between the amplifier input node and a reference node.

4. The apparatus of claim 3, wherein the capacitor network includes a third capacitor and a fourth capacitor configured to alternately form the feedback path and an additional reference path of third and fourth arrangements of the plurality of arrangements to generate a third residue signal and a fourth residue signal of the plurality of residue signals, the additional reference path including a path between the amplifier input node and an additional reference node.

5. The apparatus of claim 4, wherein the third and fourth capacitors are configured to store a value of the first residue signal and a value of the second residue signal when the amplifier and capacitor network are arranged in the first and second arrangements, and wherein the first and second capacitors are configured to store a value of the third residue signal and a value of the fourth residue signal when the amplifier and capacitor network are arranged in the third and fourth arrangements.

6. The apparatus of claim 5, wherein the first module is configured to generate the first residue signal before the third residue signal, to generate the third residue signal before the second residue signal, and to generate the second residue signal before the fourth residue signal.

9. An analog-to-digital converter comprising:

an amplifier including a first amplifier input node, a second amplifier input node, and an amplifier output node; and

a capacitor network including a first capacitor network portion and a second capacitor network portion, each of the first and second capacitor network portions including;

a first capacitor configured to couple to the first amplifier input node via a first path, to couple to the second amplifier input node via a second path, to couple to the amplifier output node via at least one of a third path and a fourth path, to couple to a selected one of a first reference node and a second reference node via a fifth path, and to couple to an input node via a sixth path; and

a second capacitor configured to couple to the first amplifier input node via the first path, to couple to the second amplifier input node via the second path, to couple to the amplifier output node via at least one of a seventh path and an eighth path, to couple to the selected one of the first reference node and the second reference node via a ninth path, and to couple to the input node via a tenth path.

10. The analog-to-digital converter of claim 9 further comprising a selector circuit configured to couple the input node of the first capacitor network portion to an additional node to receive a sample when the selector circuit is in a first mode, and to couple the input node of the second capacitor network portion to the additional node to receive the sample when the selector circuit is in a second mode.

11. The analog-to-digital converter of claim 9 further comprising a reset circuit to reset the amplifier only one time during conversion of a sample received at the input node of one of the first and second capacitor network portions.

12. The analog-to-digital converter of claim 9, wherein each of the first, second, third, fourth, fifth, sixth, seven, eighth, ninth, and tenth paths includes a switch.

13. The analog-to-digital converter of claim 9, wherein the first capacitor of the first capacitor network portion of is configured to couple to the first amplifier input node during a first duration of a period of a clock signal, and wherein the first capacitor of the second capacitor network portion of is configured to couple to the first amplifier input node during a second duration of the same period of the clock signal.

14. The analog-to-digital converter of claim 9, wherein the capacitor network further includes a third capacitor network portion and a fourth capacitor network portion, and wherein the first, second, third, and fourth capacitor network portions form a differential capacitor network.

15-21. -21. (canceled)