DISPLAY CONTROLLER, GRAPHICS PROCESSOR, RENDERING PROCESSING APPARATUS, AND RENDERING CONTROL METHOD

• US 20090225088A1
• Filed: 11/30/2006
• Published: 09/10/2009
• Est. Priority Date: 04/19/2006
• Status: Active Grant

• Current Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Original Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Inventors: Aoki, Sachiyo
• Granted Patent: US 8,026,919 B2
• Time in Patent Office: Days
• US Class Current: 345/501
• CPC Class Codes: G09G 2340/0435 Change or adaptation of the frame rate of the video stream
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers
• CPC Class Codes: H04N 5/46 for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 7/012 Conversion between an interlaced and a progressive signal for graphics images G09G2310/0229
• CPC Class Codes: H04N 7/0132 the field or frame frequency of the incoming video signal being multiplied by a positive integer, e.g. for flicker reduction

Abstract

When drawing data of a graphics processor is displayed on a display having a different vertical synchronization frequency, a failure occurs. A drawing processing section (32) of a graphics processor (30) selects a frame buffer (44) composed of a multibuffer where drawing data is written by sequentially switching the frame buffer (44). A disc controller (50) sequentially switches frame buffers (44), selects a frame buffer (44) from which the drawing data is read, and supplies the read drawing data read by scanning the inside of the frame buffer to a display. A switch signal generating section (36) generates a buffer switch signal used to indicate the switching timing of the frame buffer (44) to be read to the display controller (50). The frequency of the buffer switch is different from the vertical synchronization frequency of the display (60).

Claims

1. A display controller operative to switchably select one of a plurality of frame buffers, each of which is adapted to hold a frame of rendering data, according to a sequence, and to supply the rendering data read by scanning the selected frame buffer to a display, wherein the rendering data supplied to the display is scanned and read from the frame buffer, which is switchably selected based on a dummy vertical synchronization signal that is independent of a synchronization signal of the display.

2. The display controller according to claim 1, wherein the dummy vertical synchronization signal is a signal generated at a vertical synchronization frequency assumed by a graphics processor when generating the rendering data frame by frame.

3. The display controller according to claim 2, wherein the display controller receives the dummy vertical synchronization signal from the graphics controller and controls the timing of switching between the frame buffers according to the dummy vertical synchronization signal.

4. A graphics processor operative to supply a buffer switching signal for timing switching between a plurality of frame buffers, each of which is adapted to hold a frame of rendering data, to a display controller which switchably selects one of the frame buffers according to a sequence, and supplies the rendering data read by scanning the selected frame buffer to a display, wherein the graphics processor determines whether a vertical synchronization frequency which the graphics processor assumes when generating the rendering data frame by frame matches an actual vertical synchronization frequency of the display, and when the frequencies do not match, generates the buffer switching signal at the assumed vertical synchronization frequency, and when the frequencies match, generates the buffer switching signal at the actual vertical synchronization frequency of the display.

5. A rendering processing apparatus comprising:

a plurality of frame buffers each of which is operative to hold a frame of rendering data;

a rendering processing unit operative to switchably select a frame buffer in which to write rendering data from the plurality of frame buffers according to a sequence, and to generate the rendering data in the selected frame buffer in which to write;

a display controller operative to switchably select a frame buffer from which to read rendering data from the plurality of buffers according to a sequence, and to supply to a display the rendering data read by scanning the selected frame buffer from which to read; and

a switching signal generating unit operative to generate a buffer switching signal directing the display controller to switch the frame buffer from which to read, wherein

the switching signal generating unit generates the buffer switching signal according to the dummy vertical synchronization signal that is independent of a synchronization signal of the display.

6. The rendering processing apparatus according to claim 5, wherein the buffer switching signal is also used to direct the rendering processing unit to switch the frame buffer in which to write.

7. The rendering processing apparatus according to claim 5, wherein the switching signal generating unit generates the buffer switching signal at a frequency of a dummy synchronization signal generated at a vertical synchronization frequency which the rendering processing unit assumes when generating rendering data frame by frame.

10. The rendering processing apparatus according to claim 6, wherein the switching signal generating unit generates the buffer switching signal at a frequency of a dummy synchronization signal generated at a vertical synchronization frequency which the rendering processing unit assumes when generating rendering data frame by frame.

8. A rendering processing apparatus comprising:

a plurality of frame buffers each of which is operative to hold a frame of rendering data;

a rendering processing unit operative to switchably select a frame buffer in which to write the rendering data according to a sequence, and to generate the rendering data in the selected frame buffer in which to write;

a display controller operative to switchably select a frame buffer from which to read rendering data according to a sequence, and to supply to a display the rendering data read by scanning the selected frame buffer from which to read; and

a switching signal generating unit operative to generate a buffer switching signal directing the display controller to switch the frame buffer from which to read, wherein

the switching signal generating unit determines whether a vertical synchronization frequency which the rendering processing unit assumes when generating the rendering data frame by frame matches an actual vertical synchronization frequency of the display, and when the frequencies do not match, generates the buffer switching signal at the assumed vertical synchronization frequency, and when the frequencies match, generates the buffer switching signal at the actual vertical synchronization frequency of the display.

9. A rendering control method adapted for a display controller operative to switchably select one of a plurality of frame buffers, each of which is adapted to hold a frame of rendering data according to a sequence, and to supply the rendering data read by scanning the selected frame buffer to a display, wherein the timing of switching the frame buffer scanned by the display controller is controlled in accordance with a dummy vertical synchronization signal that is independent of a synchronization signal of the display.