Liquid Crystal Display Device

• US 20090225251A1
• Filed: 03/05/2009
• Published: 09/10/2009
• Est. Priority Date: 03/06/2008
• Status: Abandoned Application

• Current Assignee: Panasonic Liquid Crystal Display Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Hitachi Displays Limited (Japan Display Incorporated)
• Inventors: Kaitoh, Takuo, Sonoda, Daisuke, Nitta, Hidekazu
• Application Number:
  US12/398,274
• Publication Number:
  US 20090225251A1
• Time in Patent Office: Days
• US Class Current: 349/46
• CPC Class Codes: G02F 1/1303 Apparatus specially adapted to the manufacture of LCDs
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2202/103 a-Si
• CPC Class Codes: G02F 2202/104 poly-Si
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence

Abstract

In bottom-gate-type thin film transistors used in a liquid crystal display device, a channel stopper layer is formed on a poly-Si layer thus stabilizing a characteristic of the thin film transistor. The channel stopper layer is formed into a desired shape by wet etching, and the poly-Si layer is formed into a desired shape by dry etching. By applying side etching to the channel stopper layer, a peripheral portion of the poly-Si layer is exposed from the channel stopper layer, and this region is brought into contact with an n+Si layer. Due to such constitution, ON resistance of the thin film transistor can be decreased thus increasing an ON current which flows in the thin film transistor.

Claims

1. A liquid crystal display device including a display region in which pixel electrodes and thin film transistors are formed in a matrix array and a drive circuit which is formed on the periphery of the display region and includes a thin film transistor therein, wherein

the thin film transistors are configured such that a gate insulation film is formed so as to cover a gate electrode, a poly-Si layer is formed on the gate insulation film, a channel stopper layer is formed on a main surface of the poly-Si layer except for a peripheral portion of the main surface of the poly-Si layer, an n+Si layer is in contact with the peripheral portion of the main surface of the poly-Si layer, and a source/drain electrode is formed so as to cover the n+Si layer.

2. A liquid crystal display device according to claim 1, wherein the n+Si layer and the source/drain electrode cover a portion of the channel stopper layer.

3. A liquid crystal display device including a display region in which pixel electrodes and pixel-use thin film transistors are formed in a matrix array and a drive circuit which is formed on the periphery of the display region and includes a drive-circuit-use thin film transistor, wherein

the drive-circuit-use thin film transistor and the pixel-use thin film transistors are configured such that a gate insulation film is formed so as to cover a gate electrode, a semiconductor layer is formed on the gate insulation film, a channel stopper layer is formed on a main surface of the semiconductor layer except for a peripheral portion of the main surface of the semiconductor layer, an n+Si layer is in contact with the peripheral portion of the main surface of the semiconductor layer, a source/drain electrode is formed so as to cover the n+Si layer, the semiconductor layer of the drive-circuit-use thin film transistor is formed using poly-Si, and the semiconductor layer of the pixel-use thin film transistor is formed using a-Si.

4. A liquid crystal display device according to claim 3, wherein a film thickness of the a-Si film is 70 nm or below.

5. A liquid crystal display device according to claim 3, wherein the n+Si layer and the source/drain electrode cover a portion of the channel stopper layer.

6. A liquid crystal display device including a display region in which pixel electrodes and thin film transistors are formed in a matrix array and a drive circuit which is formed on the periphery of the display region and includes a thin film transistor therein, wherein

the thin film transistors are configured such that a gate insulation film is formed so as to cover a gate electrode, a poly-Si layer is formed on the gate insulation film, a channel stopper layer is formed on the poly-Si layer, and an n+Si layer and a source/drain electrode are formed so as to cover the channel stopper layer and a portion of the poly-Si layer,

the channel stopper layer is formed into a desired shape by wet etching,

the poly-Si layer is formed into a desired shape by dry etching, and

an edge portion of the poly-Si layer formed into a desired shape by dry etching is arranged outside an edge portion of the channel stopper layer formed into a desired shape by wet etching.

7. A liquid crystal display device according to claim 6, wherein the n+Si layer is formed into a desired shape by dry etching.