Data and Power System Based on CMOS Bridge
First Claim
1. A signal processing circuit comprising:
- an input inverter and an output inverter, each inverter having;
a signal input for receiving an input rectangular signal,a signal output for providing an inverted output rectangular signal, anda pair of voltage outputs for developing a rectified dc output voltage;
a first circuit input terminal connected to the output of the input inverter and the input of the output inverter;
a second circuit input terminal connected to the input of the input inverter and the output of the output inverter, wherein the signal input terminals receive an input signal having a data component;
a pair of supply voltage output terminals connected to the voltage output terminals of the inverters for providing a rectified dc supply voltage output;
a first circuit output terminal connected to one of the supply voltage output terminals; and
a second circuit output terminal connected to the second circuit input terminal, wherein the circuit output terminals provide an output signal including the data component.
1 Assignment
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Accused Products
Abstract
A signal processing circuit includes an input inverter and an output inverter. Each inverter has a signal input for receiving an input rectangular signal, a signal output for providing an inverted output rectangular signal, and a pair of voltage outputs for developing a rectified dc output voltage. A first circuit input terminal is connected to the output of the input inverter and the input of the output inverter. A second circuit input terminal is connected to the input of the input inverter and the output of the output inverter, wherein the signal input terminals receive an input signal having a data component. A pair of supply voltage output terminals is connected to the voltage output terminals of the inverters for providing a rectified dc supply voltage output. A first circuit output terminal is connected to one of the supply voltage output terminals, and a second circuit output terminal connected to the second circuit input terminal, wherein the circuit output terminals provide an output signal including the data component.
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Citations
42 Claims
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1. A signal processing circuit comprising:
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an input inverter and an output inverter, each inverter having; a signal input for receiving an input rectangular signal, a signal output for providing an inverted output rectangular signal, and a pair of voltage outputs for developing a rectified dc output voltage; a first circuit input terminal connected to the output of the input inverter and the input of the output inverter; a second circuit input terminal connected to the input of the input inverter and the output of the output inverter, wherein the signal input terminals receive an input signal having a data component; a pair of supply voltage output terminals connected to the voltage output terminals of the inverters for providing a rectified dc supply voltage output; a first circuit output terminal connected to one of the supply voltage output terminals; and a second circuit output terminal connected to the second circuit input terminal, wherein the circuit output terminals provide an output signal including the data component. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A signal processing circuit comprising:
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a CMOS bridge rectifier circuit including; a first input terminal and a second input terminal for receiving a rectangular wave form that includes a data sequence; a first output terminal and a second output terminal for providing a rectified dc output voltage; and a first data output terminal connected to one of the first and the second input terminals, and a second data output terminal connected to one of the first and the second output terminals, wherein the data output terminals provide an output signal representative of the data sequence. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A method of providing data and power in a medical implant, the method comprising:
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applying a rectangular wave input signal between a first input terminal and a second input terminal, a first switch coupled between the first input terminal and a first node, a second switch coupled between the second input terminal and the first node, the first node coupled to a first output terminal, a third switch coupled between the first input terminal and a second node, a fourth switch coupled between the second input terminal and the second node;
the second node coupled to a second output terminal, a third output terminal coupled to the second input terminal, and a fourth output terminal coupled to the second node;wherein the first switch and fourth switch are gated on when the input signal is of a first polarity; and
wherein the second switch and the third switch are gated on when the input signal is of a second polarity opposite the first polarity so that the first and second output terminals provide a dc voltage, and the third and fourth terminals provide a data component. - View Dependent Claims (18, 19, 20, 21, 22)
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23. A method of providing data and power in a medical implant, the method comprising:
applying a rectangular wave form that includes a data sequence across a first input terminal and a second input terminal of a CMOS bridge rectifier, the CMOS bridge rectifier including a first output terminal and a second output terminal for providing a rectified dc output voltage, wherein a first data output terminal connected to one of the first and the second input terminals, and a second data output terminal connected to one of the first and the second output terminals, the data output terminals providing an output signal representative of the data sequence. - View Dependent Claims (24, 25, 26, 27, 28)
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29. A method of signal processing, the method comprising:
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generating at a first component a rectangular wave form; transmitting the rectangular wave form to an implanted second component via a wired interface between the first component and the second component, the second component including a CMOS bridge rectifier; and applying the rectangular wave form across a first input terminal and a second input terminal of the CMOS bridge rectifier, the CMOS bridge rectifier including a first output terminal and a second output terminal for providing a rectified power component, wherein a substantially resistive load is operatively coupled between the first and second output terminals, the resistive load without a discrete parallel capacitor. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37)
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38. A system for signal processing, the system comprising:
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a first component for generating and transmitting a rectangular wave form; a second component including a CMOS bridge rectifier, the second component receiving the rectangular wave form from the first component via a wired interface between the first component and the second component, the CMOS bridge rectifier including a first input terminal and a second input terminal for receiving the rectangular wave form, the CMOS bridge rectifier further including a first output terminal and a second output terminal for providing a rectified power component, wherein a substantially resistive load is operatively coupled between the first and second output terminals, the resistive load without a discrete parallel capacitor. - View Dependent Claims (39, 40, 41, 42)
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Specification