LOW COST, HIGH-DENSITY RECTIFIER MATRIX MEMORY

• US 20090225579A1
• Filed: 11/05/2008
• Published: 09/10/2009
• Est. Priority Date: 11/05/2007
• Status: Active Grant

• Current Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Contour Semiconductor, Inc.
• Inventors: Shepard, Daniel R., Langdo, Thomas A., Pitera, Arthur J.
• Granted Patent: US 7,933,133 B2
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: G11C 13/00 Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A high-density memory device is fabricated three-dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.

Claims

1. An electronic memory device comprising a plurality of layers of circuitry, wherein:

a first layer comprises storage circuitry for storing and facilitating retrieval of information;

a second layer comprises decoding circuitry for selecting information in the storage circuitry; and

a third layer comprises a plurality of buffer drivers for providing an encoded signal to the decoding circuitry.

2. The electronic memory device of claim 1, wherein the first layer and the third layer are different layers.

3. The electronic memory device of claim 1, wherein the third layer comprises a substrate disposed beneath the first layer.

4. The electronic memory device of claim 3, wherein the first layer is connected to the third layer by conductive vias.

5. The electronic memory device of claim 1, wherein each of the plurality of buffer drivers comprises a transistor.

6. The electronic memory device of claim 5, wherein each of the plurality of buffer drivers consists essentially of a transistor.

7. The electronic memory device of claim 5, wherein each transistor is an NMOS transistor.

8. The electronic memory device of claim 5, wherein each transistor is a thin-film transistor.

9. The electronic memory device of claim 1, further comprising a plurality of additional first layers and a plurality of additional second layers, at least some of the first layers and at least some of the second layers residing on a single physical layer.

10. The electronic memory device of claim 1, wherein the storage circuitry for storing and facilitating retrieval of information comprises:

a first plurality of generally parallel conductors;

a second plurality of generally parallel conductors overlapping and generally orthogonal to the first plurality of generally parallel conductors; and

a plurality of nonlinear conductive devices, each device connected to the first plurality of generally parallel conductors at approximately a point of overlap between the first and second pluralities of generally parallel conductors.

11. The electronic memory device of claim 10, wherein at least one of the plurality of nonlinear conductive devices is connected to the second plurality of generally parallel conductors at approximately a point of overlap between the first and second pluralities of generally parallel conductors.

12. The electronic memory device of claim 10, wherein each of the plurality of nonlinear conductive devices comprises a diode, a fuse, an antifuse, or a phase-change material.

13. The electronic memory device of claim 10, wherein the decoding circuitry comprises:

circuitry for causing a first voltage on a selected one of the first plurality of generally parallel conductors to differ from voltages on the others of the first plurality of generally parallel conductors; and

circuitry for causing a second voltage on a selected one of the second plurality of generally parallel conductors to differ from voltages on the others of the second plurality of generally parallel conductors,

wherein (i) the first and second voltages differ sufficiently to forward bias a nonlinear conductive device at the point of overlap between the selected one of the first plurality of generally parallel conductors and the selected one of the second plurality of generally parallel conductors, and (ii) a voltage differential between the non-selected ones of the first plurality of generally parallel conductors and the non-selected ones of the second plurality of generally parallel conductors is insufficient to forward bias a nonlinear conductive device at any point of overlap therebetween.

14. The electronic memory device of claim 1, wherein the buffer drivers are connected between the circuitry for storing and facilitating retrieval of information and the decoding circuitry.