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FLASH MULTI-LEVEL THRESHOLD DISTRIBUTION SCHEME

  • US 20090225595A1
  • Filed: 05/11/2009
  • Published: 09/10/2009
  • Est. Priority Date: 09/13/2006
  • Status: Active Grant
First Claim
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1. A Flash memory device comprising:

  • a memory array having memory cells arranged in rows and columns, each memory cell erasable to have an erase threshold voltage in an erase voltage domain and programmable in a program operation to have at least one program threshold voltage in the erase voltage domain;

    a wordline driver for selectively driving a wordline connected to a gate terminal of a memory cell with a programming voltage for changing the erase threshold voltage to the at least one program threshold voltage in the erase voltage domain during the program operation.

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