Mobile nodal based communication system, method and apparatus

• US 20090225751A1
• Filed: 05/22/2007
• Published: 09/10/2009
• Est. Priority Date: 05/22/2007
• Status: Active Grant

• Current Assignee: Rockwell Collins, Inc. (Rtx Corporation)
• Original Assignee: Rockwell Collins, Inc. (Rtx Corporation)
• Inventors: Kloster, Bruce S., Koenck, Steven E., Gee, John K., Mass, Allen P., Marek, James A.
• Granted Patent: US 7,693,167 B2
• Time in Patent Office: Days
• US Class Current: 370/389
• CPC Class Codes: H04W 40/00 Communication routing or communication path finding
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

An improved micro architectural approach for a network microprocessor has low power consumption, and employs two specialized processing cores, a MAC processing core and a network processor core. Each of these processing cores has facilities designed for a specific set of functions, to handle ISO layer 2 and layer 3 functionality in a packet switched Software Defined Radio mobile network.

Claims

1. An interface controller for a node for connecting to a nodal network, the node having a routing table identifying a second node in the nodal network, the node following a communications protocol represented as an abstract model comprising a plurality of layers including a physical layer for converting data between a signal transmitted across the nodal network and a bitwise representation of the signal within the node, and a data link layer for arranging the bits of the signal into logical data, the interface controller comprising:

a physical layer interface for implementing the physical layer; and

a processing core coupled with the physical layer interface, the processing core implementing functionality of the data link layer,

wherein the core implements the data link layer functionality utilizing microoperations in the core.

2. The interface controller as claimed in claim 1, wherein the plurality of layers includes a network layer for performing network routing of the signal between the first node and the second node in the nodal network, and the interface controller further comprises a second processing core for implementing the network routing functions of the network layer, the second processing core having a core speed and accessing a RAM subsystem, a hardware address counter, and a hardware data comparator;

the RAM subsystem, the hardware address counter, and the hardware data comparator allowing the second processing core to search the routing table for a network address for the second node linearly at the core speed.

3. The interface controller as claimed in claim 1, wherein the interface controller is suitable to be held in the hand of a user.

4. The interface controller as claimed in claim 1, wherein the nodal network comprises a mobile ad-hoc network.

5. The interface controller as claimed in claim 1, wherein the physical layer interface communicates with the nodal network via Software Defined Radio (SDR).

6. The interface controller as claimed in claim 1, wherein the bitwise representation of the signal within the node comprises a data packet having a packet header including a destination field, and the nodal network utilizes at least one of wormhole routing, Asynchronous Transfer Mode (ATM) forwarding, and Multi-Protocol Label Switching (MPLS) forwarding.

7. The interface controller as claimed in claim 1, wherein the nodal network is utilized for transmitting Voice over IP (VoIP) data between the first node and the second node.

8. An interface controller for a node for connecting to a nodal network, the node having a routing table identifying a second node in the nodal network, the node following a communications protocol represented as an abstract model comprising a plurality of layers including a physical layer for converting data between a signal transmitted across the nodal network and a bitwise representation of the signal within the node, a data link layer for arranging the bits of the signal into logical data, and a network layer for performing network routing of the signal between the first node and the second node in the nodal network, the interface controller comprising:

a physical layer interface for implementing the physical layer;

a first processing core coupled with the physical layer interface, the first processing core for implementing functionality of the data link layer; and

a second processing core for implementing the network routing functions of the network layer, the second processing core having a core speed and accessing a RAM subsystem, a hardware address counter, and a hardware data comparator;

wherein the RAM subsystem, the hardware address counter, and the hardware data comparator allow the second processing core to search the routing table for a network address for the second node linearly at the core speed.

9. The interface controller as claimed in claim 8, wherein the first processing core implements the data link layer functionality utilizing microoperations in the first processing core.

10. The interface controller as claimed in claim 8, wherein the interface controller is suitable to be held in the hand of a user.

11. The interface controller as claimed in claim 8, wherein the nodal network comprises a mobile ad-hoc network.

12. The interface controller as claimed in claim 8, wherein the physical layer interface communicates with the nodal network via Software Defined Radio (SDR).

13. The interface controller as claimed in claim 8, wherein the bitwise representation of the signal within the node comprises a data packet having a packet header including a destination field, and the nodal network utilizes at least one of wormhole routing, Asynchronous Transfer Mode (ATM) forwarding, and Multi-Protocol Label Switching (MPLS) forwarding.

14. The interface controller as claimed in claim 8, wherein the first processing core and the second processing core are included on a single ASIC.

15. A system for transmitting and receiving signals across a nodal network, comprising:

a communications protocol represented as an abstract model comprising a plurality of layers including a physical layer for converting data between a signal transmitted across the nodal network and a bitwise representation of the signal within the node, a data link layer for arranging the bits of the signal into logical data, and a network layer for performing network routing of the signal between the first node and the second node in the nodal network; and

an interface controller for a node for connecting to the nodal network, the node having a routing table identifying a second node in the nodal network, the node including a physical layer interface for implementing the physical layer;

a first processing core coupled with the physical layer interface, the first processing core for implementing functionality of the data link layer utilizing microoperations wired in the first processing core; and

a second processing core for implementing the network routing functions of the network layer, the second processing core having a core speed and accessing a RAM subsystem, a hardware address counter, and a hardware data comparator;

the RAM subsystem, the hardware address counter, and the hardware data comparator allowing the second processing core to search the routing table for a network address for the second node linearly at the core speed.

16. The system as claimed in claim 15, wherein the interface controller is suitable to be held in the hand of a user.

17. The system as claimed in claim 15, wherein the nodal network comprises a mobile ad-hoc network.

18. The system as claimed in claim 15, wherein the physical layer interface communicates with the nodal network via Software Defined Radio (SDR).

19. The system as claimed in claim 15, wherein the bitwise representation of the signal within the node comprises a data packet having a packet header including a destination field, and the nodal network utilizes at least one of wormhole routing, Asynchronous Transfer Mode (ATM) forwarding, and Multi-Protocol Label Switching (MPLS) forwarding.

20. The system as claimed in claim 15, wherein the first processing core and the second processing core are included on a single ASIC.