Semiconductor device having trench-type gate and its manufacturing method capable of simplifying manufacturing steps

• US 20090227102A1
• Filed: 05/14/2009
• Published: 09/10/2009
• Est. Priority Date: 05/18/2006
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Sumida, Wataru
• Granted Patent: US 7,807,531 B2
• Time in Patent Office: Days
• US Class Current: 438/589
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In a semiconductor device, a gate silicon dioxide layer is formed within a trench of a semiconductor wafer. A first gate electrode is formed on a sidewall of the trench of the semiconductor wafer via the gate silicon dioxide layer. An insulating layer is formed on a bottom of the trench of the semiconductor wafer via the gate silicon dioxide layer and surrounded by the first gate electrode. The insulating layer excludes silicon dioxide and has different etching characteristics from those of silicon dioxide. A second gate electrode is buried in the trench of the semiconductor wafer, and is in contact with the first gate electrode and the insulating layer.

Claims

1. A method for manufacturing a semiconductor device comprising:

forming a trench in a semiconductor wafer;

forming a gate silicon dioxide layer on an entire surface of said semiconductor wafer;

depositing a first gate layer on said gate silicon dioxide layer;

etching back said first gate layer to form a first gate electrode on a sidewall of the trench of said semiconductor wafer via said gate silicon dioxide layer;

depositing an insulating layer on an entire surface of said semiconductor wafer after said first gate electrode is formed, said insulating layer excluding silicon dioxide and having different etching characteristics from those of silicon dioxide;

etching back said insulating layer using said gate silicon dioxide layer as an etching stopper, so that said insulating layer is left on a bottom of the trench of said semiconductor wafer via said gate silicon dioxide layer and is surrounded by said first gate electrode;

forming a second gate electrode layer on an entire surface of said semiconductor wafer after said insulating layer is etched back; and

etching back said second gate electrode layer using said gate silicon dioxide layer as an etching stopper to form a second gate electrode buried in the trench of said semiconductor wafer, said second gate electrode being in contact with said first gate electrode and said insulating layer.

2. The method as set forth in claim 1, wherein said semiconductor wafer comprises:

a semiconductor substrate;

an epitaxial semiconductor layer grown on said semiconductor substrate, said epitaxial semiconductor layer having the trench of said semiconductor wafer.

3. The method as set forth in claim 1, wherein said semiconductor wafer comprises a semiconductor substrate having impurity diffusion regions,

the trench of said semiconductor wafer being formed within said impurity diffusion regions.

4. The method as set forth in claim 1, wherein said insulating layer comprises one of a silicon nitride layer and a silicon oxynitride layer.

5. The method as set forth in claim 1, wherein said first gate electrode comprises a polycrystalline silicon layer, and said second gate electrode layer comprises one of a polycrystalline silicon layer and a refractory metal layer.