METHOD AND SYSTEM FOR CALIBRATING A MULTI-MODE, MULTI-STANDARD TRANSMITTER AND RECEIVER

• US 20090227214A1
• Filed: 04/21/2009
• Published: 09/10/2009
• Est. Priority Date: 09/03/2002
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Kokozidis, Christos, Bouras, Stamatios Alexandros, Georgantas, Theodore
• Granted Patent: US 9,065,537 B2
• Time in Patent Office: Days
• US Class Current: 455/86
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22
• CPC Class Codes: H04B 1/40 Circuits
• CPC Class Codes: H04B 17/14 of the whole transmission and reception path, e.g. self-test loop-back
• CPC Class Codes: H04B 17/20 of receivers

Abstract

Methods and systems for calibrating a multi-mode, multi-standard transmitter and receiver are disclosed. Aspects of the method may include configuring calibration paths in a transceiver on a chip including a plurality of Tx and Rx paths. IP2 distortion may be calibrated for the Rx paths utilizing a phase locked loops in the chip and the configurable calibration paths. Local oscillator leakage, Rx path DC offset and RSSI, Tx and Rx I and Q mismatch, and Tx and Rx path filters may be calibrated utilizing the plurality of configurable calibration paths. Cutoff frequency of the filters in the Tx and Rx paths may be calibrated. Blocker signals may be mitigated by calibrating amplifier gains in the Rx paths. The calibration paths may include an envelope detector. Local oscillator leakage and I and Q mismatch may be mitigated utilizing pre-distortion generated by an on-chip digital signal processor in the Tx paths.

Claims

1. A method for processing signals, the method comprising:

in a multi-band, multi-standard wireless transceiver integrated on a single substrate of a chip, said multi-band, multi-standard wireless transceiver comprising a plurality of transmitter (Tx) paths and a plurality of receiver (Rx) paths;

configuring one or more calibration paths between one or more of said plurality of Tx paths and one or more of said plurality of Rx paths; and

calibrating second-order intercept point (IP2) distortion for said one or more of said plurality of said Rx paths utilizing a plurality of phase locked loops in said chip and said one or more calibration paths.

2. The method according to claim 1, comprising calibrating local oscillator leakage utilizing one or more of said calibration paths.

3. The method according to claim 1, comprising calibrating one or more amplifier gains in said one or more of said plurality of Rx paths to mitigate blocker signals.

4. The method according to claim 1, comprising calibrating a DC offset in one or more of said RX paths utilizing said one or more calibration paths.

5. The method according to claim 1, comprising calibrating received signal strength (RSSI) for one or more of said RX paths utilizing said one or more calibration paths.

6. The method according to claim 1, comprising calibrating one or more filters in said one or more of said plurality of Tx paths and said one or more of said plurality of Rx paths utilizing one or more of said calibration paths

7. The method according to claim 6, comprising calibrating a cutoff frequency of said one or more of said filters.

8. The method according to claim 1, comprising calibrating Tx and Rx in-phase (I) and quadrature-phase (Q) mismatch utilizing one or more of said calibration paths.

9. The method according to claim 1, wherein one or more of said calibration paths comprises an envelope detector.

10. The method according to claim 1, comprising mitigating one or more of local oscillator leakage and I and Q mismatch utilizing pre-distortion generated by an on-chip digital signal processor in said one or more of said plurality of Tx paths.

11. A system for processing signals, the system comprising:

one or more circuits for use in a multi-band, multi-standard wireless transceiver on a chip, said multi-band, multi-standard wireless transceiver on a chip comprising a plurality of transmitter (Tx) paths and a plurality of receiver (Rx) paths, wherein said one or more circuits are operable to;

configure one or more calibration paths between one or more of said plurality of Tx paths and one or more of said plurality of Rx paths; and

calibrate second order intercept point (IP2) distortion for said one or more of said plurality of Rx paths utilizing a plurality of phase locked loops in said chip and said one or more calibration paths.

12. The system according to claim 11, wherein said one or more circuits are enabled to calibrate local oscillator leakage utilizing one or more of said calibration paths.

13. The system according to claim 11, wherein said one or more circuits are enabled to calibrate one or more amplifier gains in said one or more of said plurality of Rx paths to mitigate blocker signals.

14. The system according to claim 11, wherein said one or more circuits are enabled to calibrate a DC offset in one or more of said plurality of RX paths utilizing said one or more calibration paths.

15. The system according to claim 11, wherein said one or more circuits are enabled to calibrate received signal strength (RSSI) for one or more of said plurality of RX paths utilizing said one or more calibration paths.

16. The system according to claim 11, wherein said one or more circuits are enabled to calibrate one or more filters in said one or more of said plurality of Tx paths and said one or more of said plurality of Rx paths utilizing one or more of said calibration paths.

17. The system according to claim 16, wherein said one or more circuits are enabled to calibrate a cutoff frequency of said one or more of said filters.

18. The system according to claim 11, wherein said one or more circuits are enabled to calibrate Tx and Rx in-phase (I) and quadrature-phase (Q) mismatch utilizing said one or more calibration paths.

19. The system according to claim 11, wherein one or more of said calibration paths comprises an envelope detector.

20. The system according to claim 11, wherein said one or more circuits are enabled to mitigate one or more of local oscillator leakage and I and Q mismatch utilizing pre-distortion generated by an on-chip digital signal processor in said one or more of said plurality of Tx paths.