Vehicle Computer System with Audio Entertainment System
First Claim
1. A vehicle computer system comprising:
- an audio data processor;
an I/O memory;
a first memory access circuit associated with a first data source to transfer first audio data from the first data source to a first location in the I/O memory;
a second memory access circuit associated with a second data source to transfer second audio data from the second data source to a second location in the I/O memory; and
a third memory access circuit associated with the audio data processor to transfer the first and second audio data from the first and second locations in the I/O memory to the audio data processor for concurrent processing and output to one or more audio destinations.
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Accused Products
Abstract
A vehicle computer system has an audio entertainment system implemented in a logic unit and audio digital signal processor (DSP) independent from the host CPU. The audio entertainment system employs a set of ping/pong buffers and direct memory access (DMA) circuits to transfer data between different audio devices. Audio data is exchanged using a mapping overlay technique, in which the DMA circuits for two audio devices read and write to the same memory buffer. The computer system provides an audio manager API (application program interface) to enable applications running on the computer to control the various audio sources without knowing the hardware and implementation details of the underlying sound system. Different audio devices and their drivers control different functionality of the audio system, such as equalization, volume controls and surround sound decoding. The audio manager API transfers calls made by the applications to the appropriate device driver(s). The computer system also supports a speech recognition system. Speech utterances are picked up by a microphone and sampled at an internal sampling rate. However, the speech recognition system employs a lower sampling rate. The computer system converts microphone data from the higher internal sampling rate to the desired sampling rate by piggybacking the microphone data on command/message streams to an SPI (serial peripheral interface) of the audio DSP. The DSP performs normal low-pass filtering and down sampling on the data stream and then uses the SPI to send out the microphone data at the lower sampling rate.
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Citations
19 Claims
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1. A vehicle computer system comprising:
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an audio data processor; an I/O memory; a first memory access circuit associated with a first data source to transfer first audio data from the first data source to a first location in the I/O memory; a second memory access circuit associated with a second data source to transfer second audio data from the second data source to a second location in the I/O memory; and a third memory access circuit associated with the audio data processor to transfer the first and second audio data from the first and second locations in the I/O memory to the audio data processor for concurrent processing and output to one or more audio destinations. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A vehicle computer system comprising:
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an AM/FM tuner module a data memory including one or more ping/pong buffers; an audio data processor; and a logic unit configured to receive audio data from the AM/FM tuner module and one or more peripheral audio sources, the logic unit including an audio source direct memory access (DMA) circuit associated with the AM/FM tuner module and one or more other audio source DMA circuits associated with specific ones of the one or more peripheral audio sources, and further wherein the logic unit includes at least one data processor DMA circuit associated with the audio data processor, wherein each audio source DMA circuit is configured to; write audio data to a ping buffer within the data memory, while the at least one data processor DMA circuit reads audio data from a pong buffer within the data memory. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A vehicle computer system comprising:
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a data memory including one or more ping/pong buffers; a digital signal processor; and a logic unit configured to receive audio data from one or more peripheral audio sources, the logic unit including one or more audio source direct memory access (DMA) circuits associated with specific ones of the one or more peripheral audio sources, and further wherein the logic unit includes at least one data processor DMA circuit associated with the digital signal processor, wherein each audio source DMA circuit is configured to; write audio data to a ping buffer within the data memory; and wherein the at least one data processor DMA circuit is configured to; read audio data written by two or more audio source DMA circuits from a pong buffer within the data memory and transfer the audio data written by the two or more audio source DMA circuits to the digital signal processor for concurrent processing. - View Dependent Claims (16, 17, 18, 19)
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Specification