Serial Buffer To Support Rapid I/O Logic Layer Out Of order Response With Data Retransmission

• US 20090228630A1
• Filed: 03/06/2008
• Published: 09/10/2009
• Est. Priority Date: 03/06/2008
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Wang, Chi-Lie, Mo, Jason Z.
• Granted Patent: US 8,312,241 B2
• Time in Patent Office: Days
• US Class Current: 711/100
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9036 Common buffer combined with individual queues
• CPC Class Codes: H04L 49/9047 including multiple buffers, e.g. buffer pools

Abstract

Within a serial buffer, request packets are written to available memory blocks of a memory buffer, which are identified by a free buffer pointer list. When a request packet is written to a memory block, the memory block is removed from the free buffer pointer list, and added to a used buffer pointer list. Memory blocks in the used buffer pointer list are read, thereby transmitting the associated request packets from the serial buffer. When a request packet is read from a memory block, the memory block is removed from the used buffer pointer list and added to a request buffer pointer list. If a corresponding response packet is received within a timeout period, the memory block is transferred from the request buffer pointer list to the free buffer pointer list. Otherwise, the memory block is transferred from the request buffer pointer list to the used buffer pointer list.

Claims

1. A serial buffer comprising:

a buffer memory having a plurality of memory blocks, each configured to temporarily store a request packet;

a free buffer pointer list configured to identify each memory block in the memory buffer that is available to store a new request packet;

a used buffer pointer list configured to identify each memory block in the memory buffer that stores a request packet to be transferred out of the serial buffer; and

a request buffer pointer list configured to identify each memory block in the memory buffer that stores a request packet that has been transferred out of the serial buffer, but has not yet received an expected corresponding response.

2. The serial buffer of claim 1, further comprising one or more queues configured to load request packets into the buffer memory.

3. The serial buffer of claim 1, wherein the expected corresponding response comprises a response packet or an indication that a timeout period has expired.

4. The serial buffer of claim 1, wherein each of the memory blocks has a corresponding memory block address, and wherein the free buffer pointer list stores the memory block address of each memory block that is available to store a new request packet.

5. The serial buffer of claim 4, wherein the used buffer pointer list stores the memory block address of each memory block that stores a request packet to be transferred out of the serial buffer.

6. The serial buffer of claim 5, wherein the request buffer pointer list stores the memory block address of each memory block that stores a request packet that has been transferred out of the serial buffer, but has not yet received an expected corresponding response.

7. The serial buffer of claim 1, further comprising write control logic configured to write request packets only into memory blocks identified by the free buffer pointer list.

8. The serial buffer of claim 1, wherein the write control logic is further configured to append a transaction identification value to each request packet written into a memory block, wherein the transaction identification value corresponds with an address of the memory block.

9. The serial buffer of claim 1, further comprising request control logic configured to read request packets only from memory blocks identified by the used buffer pointer list.

10. The serial buffer of claim 9, wherein the request control logic is further configured to append a transaction identification value to each request packet read from a memory block, wherein the transaction identification value corresponds with an address of the memory block.

11. The serial buffer of claim 9, further comprising a request timeout timer associated with each of the memory blocks, wherein the request control logic is configured to start the request timeout timer associated with a memory block upon reading a request packet from the memory block.

12. The serial buffer of claim 11, further comprising a response handler configured to stop the timeout timer upon receiving a response packet associated with the request packet read from the memory block.

13. The serial buffer of claim 12, wherein the request control logic is further configured to re-read the request packet from the memory block upon detecting that the associated request timeout timer has expired.

14. The serial buffer of claim 1, further comprising response handler logic configured to identify response packets received by the serial buffer in response to request packets read from the memory buffer.

15. A method of operating a serial buffer comprising:

defining a plurality of memory blocks in a buffer memory, wherein each of the memory blocks has the capacity to store a request packet;

maintaining a first list of each of the memory blocks available to store a new request packet;

maintaining a second list of each of the memory blocks that stores a request packet to be transferred out of the serial buffer; and

maintaining a third list of each of the memory blocks that stores a request packet that has been transferred out of the serial buffer, but has not yet received an expected corresponding response.

16. The method of claim 15, further comprising writing request packets only to memory blocks in the first list.

17. The method of claim 15, further comprising reading request packets only from memory blocks in the second list.

18. The method of claim 15, further comprising transferring a memory block from the first list to the second list in response to writing a request packet to the memory block.

19. The method of claim 15, further comprising transferring a memory block from the second list to the third list in response to reading a request packet from the memory block.

20. The method of claim 15, further comprising transferring a memory block from the third list to the first list in response to receiving a response packet associated with a request packet read from the memory block.