HIGH-SPEED SOLID STATE STORAGE SYSTEM HAVING A HIERARCHY OF DIFFERENT CONTROL UNITS THAT PROCESS DATA IN A CORRESPONDING MEMORY AREA AND METHOD OF CONTROLLING THE SAME
First Claim
Patent Images
1. A solid state storage system comprising:
- a first control unit that distributes and transmits signals that are provided from a host interface; and
a second control unit controlled by the first control unit such that the second control unit performs an address mapping operation, an error checking/correcting operation, and a defective block managing operation on a plurality of memory chips.
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Accused Products
Abstract
A solid state storage system having a hierarchy of different control units that systematically process data in a corresponding memory area is disclosed. The solid state storage system includes
- a first control unit and at least one second control unit. The first control unit distributes and transmits external command signals that are provided from a host interface. The second control unit is controlled by the first control unit and performs an address mapping operation, an error checking/correcting operation, an ad defective block managing operation on a corresponding plurality of memory chips in the memory area.
72 Citations
16 Claims
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1. A solid state storage system comprising:
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a first control unit that distributes and transmits signals that are provided from a host interface; and a second control unit controlled by the first control unit such that the second control unit performs an address mapping operation, an error checking/correcting operation, and a defective block managing operation on a plurality of memory chips. - View Dependent Claims (2, 3, 4)
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5. A solid state storage system comprising:
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a host interface; a first control unit that responds to signals transmitted from the host interface; a buffer unit interposed between the host interface and the first control unit, such that the buffer unit buffers output signals from the host interface or output signals from the first control unit; a second control unit activated by the first control unit such that the second control unit directly controls the operation of a memory area; and the memory area controlled by the second control unit and inputs/outputs data. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12)
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13. A method of controlling a solid state storage system, comprising:
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allowing a command, which is received from a host interface, to be simultaneously transmitted to a plurality of sub-control units; allowing individual sub-control units to perform an address mapping operation on corresponding memory chips; allowing individual sub-control units to perform an error checking/correcting process when an error occurs while the operation of the corresponding memory chips is performed; and allowing the individual sub-control units to execute a next command when an error does not occur while the operation of the corresponding memory chips is performed. - View Dependent Claims (14, 15, 16)
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Specification