Power Management On sRIO Endpoint

• US 20090228733A1
• Filed: 03/06/2008
• Published: 09/10/2009
• Est. Priority Date: 03/06/2008
• Status: Abandoned Application

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Wang, Chi-Lie
• Application Number:
  US12/043,940
• Publication Number:
  US 20090228733A1
• Time in Patent Office: Days
• US Class Current: 713/500
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Clock signals used to operate core receive logic and core transmit logic within a serial buffer are dynamically enabled and disabled to minimize power consumption. A physical layer interface and an event monitor are continuously enabled to identify the start of incoming transactions. Upon detecting the start of an incoming transaction, the event monitor activates a packet retry signal, and also initiates generation of a receive clock signal within the serial buffer. By the time that the incoming transaction is re-sent, the receive clock signal is enabled, thereby enabling the associated core receive logic. Once enabled, the receive clock signal remains enabled until the period between consecutive incoming transactions exceeds a timeout period, whereupon the receive clock signal is disabled. A similar mechanism is provided to dynamically enable and disable a transmit clock signal, which enables and disables corresponding core transmit logic of the serial buffer.

Claims

1. A method of operating a serial buffer comprising:

monitoring incoming transactions to detect start-of-packet symbols;

operating core receive logic of the serial buffer in response to a receive clock signal, which is dynamically enabled and disabled; and

enabling the receive clock signal if the receive clock signal is disabled and a start-of-packet symbol is detected in an incoming transaction.

2. The method of claim 1, further comprising disabling the receive clock signal if the receive clock signal is enabled and a receive timeout period elapses between a time that the core receive logic detects an end of a received packet and a time that the core receive logic detects the start of a next received packet.

3. The method of claim 1, wherein the receive clock signal is enabled by causing a clock generator to generate the receive clock signal, and wherein the receive clock signal is disabled by causing the clock generator to stop generating the receive clock signal.

4. The method of claim 1, further comprising transmitting a retry request from the serial buffer if the receive clock signal is disabled and a start-of-packet symbol is detected in an incoming transaction.

5. The method of claim 4, wherein the retry request comprises an sRIO packet retry control symbol.

6. The method of claim 1, further comprising:

operating core transmit logic of the serial buffer in response to a transmit clock signal, which is dynamically enabled and disabled; and

enabling the transmit clock signal if the transmit clock signal is disabled and the core receive logic indicates that outgoing transactions must be transmitted from the serial buffer.

7. The method of claim 6, further comprising disabling the transmit clock signal if the transmit clock signal is enabled and a transmit timeout period elapses between a time that the core transmit logic detects an end of a transmitted packet and a time that the core transmit logic detects the start of a next transmitted packet.

8. The method of claim 6, wherein the transmit clock signal is enabled by causing a clock generator to generate the transmit clock signal, and wherein the transmit clock signal is disabled by causing the clock generator to stop generating the transmit clock signal.

9. The method of claim 1, further comprising disabling the receive clock signal by default.

10. The method of claim 6, further comprising disabling the transmit clock signal by default.

11. A serial buffer comprising:

a physical layer interface configured to receive incoming transactions, wherein the physical layer interface is enabled during normal operation of the serial buffer;

an event monitor coupled to the physical layer interface, and configured to identify start-of-packet symbols in the incoming transactions, wherein the event monitor is enabled during normal operation of the serial buffer;

core receive logic coupled to receive the incoming transactions from the physical layer interface; and

clock enable logic coupled to the event monitor, and configured to dynamically enable and disable a receive clock signal provided to the core receive logic, wherein the receive clock signal, when enabled, enables the core receive logic to process incoming transactions received from the physical layer interface.

12. The serial buffer of claim 11, further comprising core transmit logic coupled to the physical layer interface, wherein the clock enable logic is configured to dynamically enable and disable a transmit clock signal provided to the core transmit logic, wherein the transmit clock signal, when enabled, enables the core transmit logic to control the transmission of outgoing transactions to the physical layer interface.

13. The serial buffer of claim 11, further comprising a receive timer configured to cause the clock enable logic to disable the receive clock signal upon determining that a receive timeout period has expired.

14. A serial buffer comprising:

means for monitoring incoming transactions to detect start-of-packet symbols;

means for disabling a receive clock signal used to operate core receive logic of the serial buffer; and

means for enabling the receive clock signal if the receive clock signal is currently disabled and a start-of-packet symbol is detected in an incoming transaction.

15. The serial buffer of claim 14, wherein the means for disabling the receive clock signal are configured to disable the receive clock signal if the receive clock signal is currently enabled and a receive timeout period elapses between an end of an incoming transaction and a start of a next incoming transaction.

16. The serial buffer of claim 14, wherein the means for enabling the receive clock signal comprise a clock generator configured to generate the receive clock signal.

17. The serial buffer of claim 14, further comprising means for transmitting a retry request from the serial buffer if the receive clock signal is currently disabled and a start-of-packet symbol is detected in an incoming transaction.

18. The serial buffer of claim 14, further comprising:

means for disabling a transmit clock signal used to operate core transmit logic of the serial buffer; and

means for enabling the transmit clock signal if the transmit clock signal is currently disabled and the core receive logic indicates that outgoing transactions must be transmitted from the serial buffer.

19. The method of claim 18, wherein the means for disabling the transmit clock signal are configured to disable the transmit clock signal if the transmit clock signal is currently enabled and a transmit timeout period elapses between an end of an outgoing transaction and a start of a next outgoing transaction.

20. The serial buffer of claim 18, wherein the means for enabling the transmit clock signal comprise a clock generator configured to generate the transmit clock signal.