EFFICIENT READOUT FROM ANALOG MEMORY CELLS USING DATA COMPRESSION

• US 20090228761A1
• Filed: 03/04/2009
• Published: 09/10/2009
• Est. Priority Date: 03/07/2008
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Anobit Technologies, Ltd. (Apple Inc.)
• Inventors: Shalvi, Ofir, Perlmutter, Uri, Sokolov, Dotan, Golov, Oren
• Granted Patent: US 8,230,300 B2
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0638 Organizing or formatting or addressing of data
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A method for data storage includes storing data in a group of analog memory cells by writing respective input storage values to the memory cells in the group. After storing the data, respective output storage values are read from the analog memory cells in the group. Respective confidence levels of the output storage values are estimated, and the confidence levels are compressed. The output storage values and the compressed confidence levels are transferred from the memory cells over an interface to a memory controller.

Claims

1. A method for data storage, comprising:

storing data in a group of analog memory cells by writing respective input storage values to the memory cells in the group;

after storing the data, reading respective output storage values from the analog memory cells in the group;

estimating respective confidence levels of the output storage values;

compressing the confidence levels; and

transferring the output storage values and the compressed confidence levels from the memory cells over an interface to a memory controller.

2. The method according to claim 1, and comprising decompressing the transferred output storage values at the memory controller, and reconstructing the data responsively to the output storage values and the decompressed confidence levels.

3. The method according to claim 2, wherein storing the data comprises encoding the data with an Error Correction Code (ECC), and wherein reconstructing the data comprises decoding the ECC responsively to the decompressed confidence levels.

4. The method according to claim 3, wherein decoding the ECC comprises computing respective ECC metrics of the output storage values responsively to the confidence levels, and decoding the ECC responsively to the ECC metrics.

5. The method according to claim 4, and comprising refining at least some of the confidence levels, updating the ECC metrics based on the refined confidence levels and re-decoding the ECC responsively to the updated ECC metrics.

6. The method according to claim 5, wherein refining the confidence levels and updating the ECC metrics comprise:

at a first time, refining the confidence levels and updating the ECC metrics only responsively to a failure in decoding the ECC; and

at a second time subsequent to the first time, refining the confidence levels and updating the ECC metrics before initially attempting to decode the ECC.

7. The method according to claim 5, wherein refining the confidence levels comprises refining the confidence levels of only a subset of the output storage values that were previously identified as having a low confidence level.

8. The method according to claim 4, wherein computing the ECC metrics comprises marking some of the output storage values as erasures.

9. The method according to claim 1, wherein reading the output storage values comprises applying one or more first read thresholds to the analog memory cells in the group, and wherein estimating the confidence levels comprises re-reading the analog memory cells in the group using one or more second read thresholds, different from the first read thresholds.

10. The method according to claim 9, wherein storing the data comprises programming each of the analog memory cells in the group to a respective programming state selected from two or more programming states, and wherein re-reading the analog memory cells comprises identifying the output storage values contained in a boundary region separating two of the programming states.

11. The method according to claim 1, wherein reading the output storage values comprises re-reading the output storage values multiple times to produce respective multiple sets of read results, and wherein estimating the confidence levels comprises determining differences between the respective read results in the multiple sets.

12. The method according to claim 11, wherein re-reading the output storage values comprises producing a first set of the read results using a first read operation having a first accuracy level, and producing a second set of the read results using a second read operation having a second accuracy level, finer than the first accuracy level.

13. The method according to claim 1, wherein estimating the confidence levels comprises assigning some of the output storage value a low confidence level, and wherein compressing and transferring the confidence levels comprise indicating to the memory controller only the output storage values having the low confidence level.

14. The method according to claim 13, wherein the interface comprises a parallel bus having a signaling line, wherein transferring the output storage values comprises sending one or more of the output storage values during each cycle of the bus, and wherein indicating the storage values having the low confidence level comprises signaling over the signaling line when at least one of the output storage values sent during a given cycle has the low confidence level.

15. The method according to claim 13, wherein the interface comprises a parallel bus having a signaling line, wherein indicating the storage values having the low confidence level comprises sending the storage values having the low confidence level over the signaling line, and wherein transferring the output storage values comprises sending the output storage values over lines other than the signaling line.

16. Apparatus for data storage, comprising:

a plurality of analog memory cells; and

circuitry, which is coupled to store data in a group of the analog memory cells by writing respective input storage values to the memory cells in the group, to read respective output storage values from the analog memory cells in the group after storing the data, to estimate respective confidence levels of the output storage values, to compress the confidence levels, and to transfer the output storage values and the compressed confidence levels from the memory cells over an interface to a memory controller.

17. The apparatus according to claim 16, wherein the circuitry is coupled to read the output storage values by applying one or more first read thresholds to the analog memory cells in the group, and to estimate the confidence levels by re-reading the analog memory cells in the group using one or more second read thresholds, different from the first read thresholds.

18. The apparatus according to claim 17, wherein the circuitry is coupled to store the data by programming each of the analog memory cells in the group to a respective programming state selected from two or more programming states, and to estimate the confidence levels by identifying, using the second read thresholds, the output storage values contained in a boundary region separating two of the programming states.

19. The apparatus according to claim 16, wherein the circuitry is coupled to re-read the output storage values multiple times to produce respective multiple sets of read results, and to estimate the confidence levels by determining differences between the respective read results in the multiple sets.

20. The apparatus according to claim 19, wherein the circuitry is coupled to produce a first set of the read results using a first read operation having a first accuracy level, and to produce a second set of the read results using a second read operation having a second accuracy level, finer than the first accuracy level.

21. The apparatus according to claim 16, wherein the circuitry is coupled to assign some of the output storage value a low confidence level, and to indicate to the memory controller only the output storage values having the low confidence level.

22. The apparatus according to claim 21, wherein the interface comprises a parallel bus comprising a signaling line, and wherein the circuitry is coupled to send one or more of the output storage values during each cycle of the bus, and to signal over the signaling line when at least one of the output storage values sent during a given cycle has the low confidence level.

23. The apparatus according to claim 21, wherein the interface comprises a parallel bus comprising a signaling line, and wherein the circuitry is coupled to send the storage values having the low confidence level over the signaling line and to send the output storage values over lines other than the signaling line.

24. Apparatus for data storage, comprising:

a memory device, comprising;

a plurality of analog memory cells; and

circuitry, which is coupled to store data in a group of the analog memory cells by writing respective input storage values to the memory cells in the group, to read respective output storage values from the analog memory cells in the group after storing the data, to estimate respective confidence levels of the output storage values, to compress the confidence levels, and to transfer the output storage values and the compressed confidence levels from the memory cells over an interface; and

a memory controller, which is configured to receive the output storage values and the compressed confidence levels over the interface, to decompress the transferred output storage values and to reconstruct the data responsively to the output storage values and the decompressed confidence levels.

25. The apparatus according to claim 24, wherein the memory controller comprises an Error Correction Code (ECC) unit, which is coupled to encode the stored data with an ECC, and to reconstruct the data by decoding the ECC responsively to the decompressed confidence levels.

26. The apparatus according to claim 25, wherein the memory controller is configured to compute respective ECC metrics of the output storage values responsively to the confidence levels, and wherein the ECC unit is coupled to decode the ECC responsively to the ECC metrics.

27. The apparatus according to claim 26, wherein the memory controller is configured to cause the circuitry to refine at least some of the confidence levels, to update the ECC metrics based on the refined confidence levels and to cause the ECC unit to re-decode the ECC responsively to the updated ECC metrics.

28. The apparatus according to claim 27, wherein the memory controller is configured, at a first time, to cause the circuitry to refine the confidence levels and to update the ECC metrics only responsively to a failure in decoding the ECC, and, at a second time subsequent to the first time, to cause the circuitry to refine the confidence levels and to update the ECC metrics before initially attempting to decode the ECC.

29. The apparatus according to claim 27, wherein the memory controller is configured to cause the circuitry to refine the confidence levels of only a subset of the output storage values that were previously identified as having a low confidence level.

30. The apparatus according to claim 26, wherein the memory controller is configured to mark some of the output storage values as erasures for the ECC unit.

31. The apparatus according to claim 24, wherein the circuitry is coupled to read the output storage values by applying one or more first read thresholds to the analog memory cells in the group, and to estimate the confidence levels by re-reading the analog memory cells in the group using one or more second read thresholds, different from the first read thresholds.

32. The apparatus according to claim 31, wherein the circuitry is coupled to store the data by programming each of the analog memory cells in the group to a respective programming state selected from two or more programming states, and to estimate the confidence levels by identifying, using the second read thresholds, the output storage values contained in a boundary region separating two of the programming states.

33. The apparatus according to claim 24, wherein the circuitry is coupled to assign some of the output storage value a low confidence level, and to indicate to the memory controller only the output storage values having the low confidence level.

34. The apparatus according to claim 33, wherein the interface comprises a parallel bus comprising a dedicated signaling line, and wherein the circuitry is coupled to send one or more of the output storage values during each cycle of the bus, and to signal over the dedicated signaling line when at least one of the output storage values sent during a given cycle has the low confidence level.