Atomic Layer Deposition of Gate Dielectric Layer with High Dielectric Constant for Thin Film Transisitor

• US 20090230389A1
• Filed: 10/14/2008
• Published: 09/17/2009
• Est. Priority Date: 03/17/2008
• Status: Abandoned Application

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Dukes, Thomas H., Chen, Zhizhang
• Application Number:
  US12/251,085
• Publication Number:
  US 20090230389A1
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/3141 Deposition using atomic layer deposition techniques [ALD]
• CPC Class Codes: H01L 21/31641 Deposition of Zirconium oxides, e.g. ZrO2
• CPC Class Codes: H01L 21/31645 Deposition of Hafnium oxides, e.g. HfO2
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Embodiments of a thin film transistor with an atomic layer deposition gate dielectric layer having a high dielectric constant and a zinc indium oxide channel are disclosed.

Claims

1. A thin film transistor (TFT) comprising:

a substrate;

a gate electrode on the substrate;

an atomic layer deposition film with a high dielectric constant on the gate electrode and the substrate;

a source connection on the film;

a drain connection on the film; and

a zinc indium oxide (ZIO) channel on the film between the source and drain connections.

2. The TFT of claim 1 wherein the high dielectric constant atomic layer deposition film is one of hafnium oxide (HfO₂) and zirconium oxide (ZrO₂).

3. The TFT of claim 1 wherein the high dielectric constant is greater than or equal to 18.

4. The TFT of claim 1 wherein the gate electrode is formed from a conductive film stack made from one of chromium/gold and chromium/aluminum.

5. The TFT of claim 1 wherein the source and the drain electrodes are formed from indium tin oxide.

6. The TFT of claim 1 further comprising:

a passivation layer on the ZIO channel.

7. A method for fabricating a thin film transistor (TFT), the method comprising:

forming a gate electrode on a substrate;

forming an atomic layer deposition gate dielectric layer with high dielectric constant on the gate electrode and the substrate;

forming source and drain electrode on the gate dielectric layer; and

forming a zinc indium oxide channel on the gate dielectric layer between the source and drain connections.

8. The method of claim 7 further comprising:

forming the gate dielectric layer by applying water vapor, applying a precursor material, and removing excess precursor material and byproducts.

9. The method of claim 8 wherein the precursor material is one of tetrakis(dimethylamido) hafnium(IV) ([(CH₃)₂N]₄Hf) and tetrakis(dimethylamido)zirconium(IV) ([(CH₃)₂N]₄Zr).

10. The method of claim 7 wherein the gate dielectric layer is one of hafnium oxide (HfO₂) and zirconium oxide (ZrO₂).

11. The method of claim 7 further comprising:

annealing the TFT at a temperature between 150°

C. and 200°

C.

12. The method of claim 7 further comprising:

forming a passivation layer on the zinc indium oxide channel.

13. The method of claim 7 further comprising:

forming the zinc indium oxide channel by sputtering zinc indium oxide.

14. The method of claim 7 further comprising:

forming the gate electrode by sputtering an electrically conductive material.

15. The method of claim 7 further comprising:

forming the source and the drain electrodes by sputtering an electrically conductive material

16. The method of claim 7 wherein the substrate is a low temperature substrate.

17. A method comprising:

providing a substrate;

providing a gate electrode on the substrate;

providing an atomic layer deposition gate dielectric layer with high dielectric constant on the gate electrode and the substrate;

providing a source connection on the gate dielectric layer;

providing a drain connection on the gate dielectric layer; and

providing a zinc indium oxide (ZIO) channel on the gate dielectric layer between the source and drain connections.

18. The method of claim 18 wherein the gate dielectric layer is one of hafnium oxide (HfO₂) and zirconium oxide (ZrO₂).

19. The method of claim 18 wherein the substrate is a low temperature substrate.

20. The method of claim 18 further comprising:

providing a passivation layer on the ZIO channel.