Semiconductor Device and Method for Manufacturing the Same

• US 20090230447A1
• Filed: 06/27/2008
• Published: 09/17/2009
• Est. Priority Date: 03/13/2008
• Status: Abandoned Application

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Hwang, Sang Min
• Application Number:
  US12/147,739
• Publication Number:
  US 20090230447A1
• Time in Patent Office: Days
• US Class Current: 257/296
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS

Abstract

A semiconductor device may include a capacitor and a transistor on a silicon-on-insulator (SOI) substrate and a method for manufacturing the semiconductor device may include forming such a structure. A semiconductor device, formed on a silicon-on-insulator structure including first and second silicon layers and a insulating layer buried between the first and the second silicon layers, may include a capacitor including one electrode formed in a doped region of the first silicon layer and the other electrode formed in a well region of the second silicon layer.

Claims

1. A semiconductor device formed on a silicon-on-insulator structure including first and second silicon layers and a insulating layer buried between the first and the second silicon layers, comprising a capacitor including a first electrode formed in a doped region of the first silicon layer and a second electrode formed in a well region of the second silicon layer.

2. The semiconductor device according to claim 1, further comprising a transistor including a gate formed on an active region of the first silicon layer and a source and a drain formed at sides of the gate in the active region.

3. The semiconductor device according to claim 2, further comprising an isolation layer, formed in a trench where the first silicon layer is removed, for defining the active region.

4. The semiconductor device according to claim 1, further comprising:

a first contact for coupling the first electrode to a first wire; and

a second contact having a slit-type shape for coupling the second electrode to a second wire.

5. The semiconductor device according to claim 4, further comprising a plug, formed in the well region, for reducing a contact resistance between the second electrode and the second contact.

6. The semiconductor device according to claim 1, wherein the well region is P type ion-doped, the plug is P+ type ion-doped, and the doped region is N+ type ion-doped.

7. The semiconductor device according to claim 1, wherein the well region is N type ion-doped, the plug is N+ type ion-doped, and the doped region is P+ type ion-doped.

8. A method for manufacturing a semiconductor device, comprising:

preparing a wafer having a silicon-on-insulator structure including first and second silicon layers and a insulating layer buried between the first and the second silicon layers, wherein the second silicon layer includes a well region as a first electrode of a capacitor; and

performing ion-implantation to the first silicon layer to form a second electrode of the capacitor.

9. The method according to claim 8, further comprising forming an isolation layer for defining the active region in a trench where the first silicon layer is removed.

10. The method according to claim 9, further comprising:

forming a gate on the active region; and

performing an ion-implantation to form a drain and a source at sides of the gate in the active region.

11. The method according to claim 8, further comprising:

forming an intervening insulation layer over the first silicon layer;

forming a first contact on the well region of the second silicon layer through the intervening insulation layer and the insulating layer; and

forming a second contact on the second electrode through the intervening insulation layer.

12. The method according to claim 11, wherein the forming a first contact includes:

etching the intervening insulation layer and the insulating layer to form a first slit-type contact hole exposing a partial portion of the well region;

performing an ion-implantation to the partial portion of the well region to form a plug; and

filling up a conductive material into the first contact hole.

13. The method according to claim 11, wherein the forming a second contact includes:

etching the intervening insulation layer to form a second contact hole exposing a partial portion of the second electrode;

performing an ion-implantation to the second electrode; and

filling up a conductive material into the second contact hole.

14. The method according to claim 11, further comprising:

forming metal wires connected the first and the second contacts over the intervening insulation layer.

15. A semiconductor device formed on a substrate including a silicon-on-insulator structure, comprising a capacitor and a transistor wherein a first electrode of the capacitor is located at a same level with a source and a drain of the transistor and a second electrode of the capacitor is located at a lower level than the source and the drain of the transistor.

16. The semiconductor device according to claim 15, wherein the first electrode of the capacitor comprises an ion-implanted partial portion of a first silicon layer on an insulator in the substrate and the second electrode of the capacitor is a well region of second silicon layer under the insulator in the substrate.

17. The semiconductor device according to claim 16, further comprising a contact connected to the second electrode of the capacitor through the insulator of the substrate for coupling the capacitor to a wire.

18. The semiconductor device according to claim 17, further comprising a plug formed in the well region of second silicon layer for reducing a resistance of a junction between the second electrode and the contact, wherein the plug has higher dopant ion-concentration than the well region.

19. A method for manufacturing a semiconductor device, comprising:

performing ion-implantation to active regions in a substrate including a silicon-on-insulator structure to thereby form a first electrode of a capacitor and a source and a drain of a transistor.

20. The method according to claim 19, further comprising:

forming a gate on a center of the active region in a transistor region; and

forming a contact coupled to a second electrode of the capacitor through the insulator of the substrate, wherein the second electrode of the capacitor is disposed in a well region of a silicon layer under the insulator.