SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

• US 20090230467A1
• Filed: 05/26/2009
• Published: 09/17/2009
• Est. Priority Date: 05/20/2005
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Nakazawa, Yoshito, Yatsuda, Yuji
• Granted Patent: US 7,834,407 B2
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n⁺-type semiconductor region of the protective diode are formed in the same step.

Claims

1. A semiconductor device including a field-effect transistor and a diode formed over the same semiconductor substrate, the semiconductor device comprising:

a drain region of said field-effect transistor formed over the semiconductor substrate;

a channel forming region of said field-effect transistor formed over the drain region;

a source region of said field-effect transistor formed over the channel forming region;

a trench reaching the drain region from an upper surface of the source region;

a first insulating film formed in the trench;

a first conductive film formed over the first insulating film in the trench;

a gate insulating film of said field-effect transistor formed over the first insulating film in the trench;

a gate electrode of said field-effect transistor formed over the gate insulating film in the trench;

a second conductive film made of the same film as the first conductive film, and formed over the semiconductor substrate; and

an anode region and a cathode region of the diode formed in the second conductive film,

wherein each of the anode region and the cathode region of the diode is electrically connected to the gate electrode or the source region of the field-effect transistor.

2. The semiconductor device according to claim 1,

wherein a plurality of cathode regions are formed in the second conductive film,

wherein said anode region is disposed in contact with the plurality of cathode regions among the plurality of cathode regions,

wherein one of the plurality of cathode regions is electrically connected to the gate electrode of the field-effect transistor, and

wherein the other one of the plurality of cathode regions is electrically connected to the source region of the field-effect transistor.

3. The semiconductor device according to claim 1,

wherein the gate electrode, and the first and second conductive films are made of polycrystalline silicon films, and

wherein the resistance of the gate electrode is lower than that of the first conductive film.

4. The semiconductor device according to claim 1, wherein the gate electrode and the first conductive film are electrically connected to each other.

5. The semiconductor device according to claim 1, wherein the thickness of the first insulating film is larger than that of the gate insulating film.

6. A semiconductor device comprising:

(a) a field-effect transistor having a trench gate structure with a dummy gate electrode; and

(b) a protective diode,

wherein the field-effect transistor and the protective diode are formed over the same semiconductor substrate.

7. The semiconductor device according to claim 6, wherein a cathode region of the protective diode is connected to the gate electrode of the field-effect transistor, and an anode region of the protective diode is connected to a source region of the field-effect transistor.

8. The semiconductor device according to claim 6, wherein the anode region of the protective diode is connected to the gate electrode of the field-effect transistor, and the cathode region of the protective diode is connected to the source region of the field-effect transistor.

9. The semiconductor device according to claim 6, wherein a plurality of protective diodes are connected between the gate electrode and the source region of the field-effect transistor.

10. The semiconductor device according to claim 9, wherein one cathode region of the plurality of protective diodes whose anode regions are connected to each other is connected to the gate electrode of the field-effect transistor, and the other cathode region thereof is connected to the source region of the field-effect transistor.

11. The semiconductor device according to claim 6, wherein a polycrystalline silicon film for the protective diode included in the protective diode is formed in the same step as that of a polycrystalline silicon film for the dummy gate electrode included in the dummy gate electrode.

12. The semiconductor device according to claim 6, wherein a cathode region of the protective diode is formed in the same step as that of the source region of the field-effect transistor.

13. The semiconductor device according to claim 6, wherein a concentration of impurities introduced in the dummy gate electrode is lower than that of impurities introduced in the gate electrode of the field-effect transistor.

14. The semiconductor device according to claim 6, wherein a resistance of the dummy gate electrode is larger than that of the gate electrode of the field-effect transistor.

15. The semiconductor device according to claim 6, wherein a thickness of a lead-out part for the dummy gate electrode is smaller than that of a lead-out part for the gate electrode of the field-effect transistor.

16. The semiconductor device according to claim 6, wherein the dummy gate electrode and the gate electrode of the field-effect transistor are electrically connected to each other.

17. The semiconductor device according to claim 6, wherein a first contact hole connected to the dummy gate electrode and a second contact hole connected to the gate electrode of the field-effect transistor are arranged linearly, and a gate interconnection is disposed linearly over the first contact hole and the second contact hole.

18. The semiconductor device according to claim 6,

wherein the dummy gate electrode is connected to the source region of the field-effect transistor, and

wherein the first contact hole connected to the dummy gate electrode and the second contact hole connected to the gate electrode of the field-effect transistor are arranged linearly, and in a position where a source electrode over the first contact hole is formed in a recessed shape, the corresponding gate interconnection over the second contact hole is formed in a convex shape, while, in a position where the source electrode is formed in a convex shape, the corresponding gate interconnection is formed in a recessed shape.

19. A method of manufacturing a semiconductor device, the semiconductor device including:

a field-effect transistor having a trench gate structure with a dummy gate electrode; and

a protective diode,

the method comprising a step of;

forming a polycrystalline silicon film for the protective diode, which is included in the protective diode, and a polycrystalline silicon film for the dummy gate electrode, which is included in the dummy gate electrode, in the same step.

20. The method according to claim 19, further comprising a step of:

forming the cathode region of the protective diode and the source region of the field-effect transistor in the same step.