Leadframe package with dual lead configurations

• US 20090230520A1
• Filed: 05/26/2009
• Published: 09/17/2009
• Est. Priority Date: 11/12/2004
• Status: Abandoned Application

• Current Assignee: Jong-Joo Lee, Mee-Hyun Ahn
• Original Assignee: Jong-Joo Lee, Mee-Hyun Ahn
• Inventors: Ahn, Mee-Hyun, Lee, Jong-Joo
• Application Number:
  US12/453,863
• Publication Number:
  US 20090230520A1
• Time in Patent Office: Days
• US Class Current: 257/666
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4826 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/4943 the connecting portions being staggered
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/4951 Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 23/49513 having bonding material between chip and die pad
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/078 : Adhesive characteristics other than chemical
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

The invention provides a variety of leadframe packages in which signal connections and fixed voltage connections are configured differently to improve the relative performance of the connections relative to their assigned function. The signal connections incorporate one or more configurations of signal lead and corresponding signal bonding wires that tend to reduce the relative capacitance of the signal connectors and thereby improve high speed performance. The fixed voltage connections incorporate configurations of fixed voltage leads and fixed voltage bonding wires that will tend to reduce the inductance of the fixed voltage connector and reduce noise on the fixed voltage connections and improve power delivery characteristics. The configurations of the associated signal and fixed voltage connections will tend to result in signal connections that include signal leads that are shorter, narrower and/or more widely separated from the active surface of the semiconductor chip than the corresponding fixed voltage leads.

Claims

1. A leadframe package comprising:

a semiconductor chip having a plurality of signal chip pads and a plurality of fixed voltage chip pads formed on an active surface;

a leadframe having a plurality of signal leads having an average length L_SL and a plurality of fixed voltage leads designated for a single voltage having an average length L_FL;

signal bonding wires having an average length L_SW electrically connecting the signal leads to corresponding signal chip pads; and

fixed voltage bonding wires having an average length L_FW electrically connecting the fixed voltage leads to corresponding fixed voltage chip pads;

wherein the average length of the signal leads L_SL and the average length of the fixed voltage leads L_FL satisfy the expression L_SL<

L_FL, and the signal leads have an average width W_SL and the fixed voltage leads have an average width W_FL that satisfy the expression W_SL<

W_F.

2. The leadframe package according to claim 1, wherein:

the average length of the signal bonding wires L_SW and the average length of the plurality of fixed voltage bonding wires L_FW satisfy the expression L_SW>

L_FW.

3. The leadframe package according to claim 1, wherein:

the signal leads have an average capacitance C_SL and the plurality of fixed voltage leads have an average capacitance C_FL that satisfy the expression C_SL<

C_FL.

4. The leadframe package according to claim 1, wherein:

a sum of the average length of the plurality of signal leads L_SL and the average length the signal bonding wires L_SW and the sum of the average length of the plurality of fixed voltage leads L_FL and the average length of the plurality of fixed voltage bonding wires L_FW satisfy the expression (L_SL+L_SW)≈

(L_FL+L_FW).

5. The leadframe package according to claim 1, wherein:

all of the signal leads extend over the active surface of the semiconductor chip; and

all of the plurality of fixed voltage leads extend over the active surface of the semiconductor chip.

6. The leadframe package according to claim 1, wherein:

the plurality of the signal leads include an inner portion that extends over the active surface of the semiconductor chip, the inner portions of the plurality of signal leads having an average area A_SL; and

the plurality of the fixed voltage leads include an inner portion that extends over the active surface of the semiconductor chip, the inner portions of the plurality of fixed voltage leads having an average area A_FL that satisfy the expression A_SL<

A_FL.

7. The leadframe package according to claim 1, wherein:

the plurality of fixed voltage leads are configured to extend between a major portion of a corresponding plurality of signal bonding wires and the active surface of the semiconductor chip.

8. The leadframe package according to claim 7, wherein:

the plurality of fixed voltage leads include an inner portion that extends over the active surface of the semiconductor chip and is separated from the active surface by an average distance D_FL; and

the plurality of signal leads include an inner portion that extends over the active surface of the semiconductor chip and is separated from the active surface by an average distance D_SL that satisfy the relationship D_FL<

D_SL.

9. The leadframe package according to claim 1, wherein:

the signal chip pads and the fixed voltage chip pads are arranged in a single row oriented along a central axis of the semiconductor chip.

10. The leadframe package according to claim 9, wherein:

the plurality of the signal leads and the plurality of fixed voltage leads extend over the active surface of the semiconductor chip and are disposed on both sides of the row of the chip pads.

11. The leadframe package according to claim 10, wherein:

an average distance between the plurality of signal leads and corresponding chip pads is greater than that between the plurality of fixed voltage leads and the chip pads.

12. The leadframe package according to claim 1, wherein:

the plurality of fixed voltage leads are configured to extend between a corresponding plurality of signal leads and a corresponding plurality of signal chip pads.

13. The leadframe package according to claim 1, wherein:

the plurality of fixed voltage leads include an opening formed in an enlarged region of the plurality of fixed voltage leads.

14. The leadframe package according to claim 1, wherein:

the plurality of fixed voltage leads include a recess formed inwardly from an edge of an enlarged region of the plurality of fixed voltage leads.

15. The leadframe package according to claim 1, wherein:

at least one of the plurality of fixed voltage leads includes an optical pattern recognition target formed in an enlarged portion of the plurality of fixed voltage leads.

16. The leadframe package according to claim 1, wherein:

a first group of the plurality of fixed voltage leads are designated for connection to a power potential and include a first optical pattern recognition target; and

a second group of the plurality of fixed voltage leads are designated for connection to a ground potential and include a second optical pattern recognition target

17. The leadframe package according to claim 9, wherein:

a first group of the plurality of fixed voltage leads are designated for connection to a power potential;

a second group of the plurality of fixed voltage leads are designated for connection to a ground potential; and

a first fixed voltage lead is electrically connected to a second fixed voltage lead selected from the same group.