Leadframe package with dual lead configurations
First Claim
1. A leadframe package comprising:
- a semiconductor chip having a plurality of signal chip pads and a plurality of fixed voltage chip pads formed on an active surface;
a leadframe having a plurality of signal leads having an average length LSL and a plurality of fixed voltage leads designated for a single voltage having an average length LFL;
signal bonding wires having an average length LSW electrically connecting the signal leads to corresponding signal chip pads; and
fixed voltage bonding wires having an average length LFW electrically connecting the fixed voltage leads to corresponding fixed voltage chip pads;
wherein the average length of the signal leads LSL and the average length of the fixed voltage leads LFL satisfy the expression LSL<
LFL, and the signal leads have an average width WSL and the fixed voltage leads have an average width WFL that satisfy the expression WSL<
WF.
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Accused Products
Abstract
The invention provides a variety of leadframe packages in which signal connections and fixed voltage connections are configured differently to improve the relative performance of the connections relative to their assigned function. The signal connections incorporate one or more configurations of signal lead and corresponding signal bonding wires that tend to reduce the relative capacitance of the signal connectors and thereby improve high speed performance. The fixed voltage connections incorporate configurations of fixed voltage leads and fixed voltage bonding wires that will tend to reduce the inductance of the fixed voltage connector and reduce noise on the fixed voltage connections and improve power delivery characteristics. The configurations of the associated signal and fixed voltage connections will tend to result in signal connections that include signal leads that are shorter, narrower and/or more widely separated from the active surface of the semiconductor chip than the corresponding fixed voltage leads.
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Citations
17 Claims
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1. A leadframe package comprising:
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a semiconductor chip having a plurality of signal chip pads and a plurality of fixed voltage chip pads formed on an active surface; a leadframe having a plurality of signal leads having an average length LSL and a plurality of fixed voltage leads designated for a single voltage having an average length LFL; signal bonding wires having an average length LSW electrically connecting the signal leads to corresponding signal chip pads; and fixed voltage bonding wires having an average length LFW electrically connecting the fixed voltage leads to corresponding fixed voltage chip pads; wherein the average length of the signal leads LSL and the average length of the fixed voltage leads LFL satisfy the expression LSL<
LFL, and the signal leads have an average width WSL and the fixed voltage leads have an average width WFL that satisfy the expression WSL<
WF. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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Specification