SEMICONDUCTOR MODULE

• US 20090230535A1
• Filed: 03/12/2008
• Published: 09/17/2009
• Est. Priority Date: 03/12/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Strack, Helmut, Hoeglauer, Josef, Otremba, Ralf, Schloegel, Xaver
• Granted Patent: US 8,637,341 B2
• Time in Patent Office: Days
• US Class Current: 257/690
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/2518 being disposed on at least two different sides of the body, e.g. dual array
• CPC Class Codes: H01L 2224/73153 Bump and layer connectors
• CPC Class Codes: H01L 2224/76155 Jetting means, e.g. ink jet
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/82001 involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2224/82039 using a laser
• CPC Class Codes: H01L 2224/82047 by mechanical means, e.g. severing, pressing, stamping
• CPC Class Codes: H01L 2224/82102 using jetting, e.g. ink jet
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3157 Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 24/25 of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/1815 : Shape

Abstract

A semiconductor module. In one embodiment, at least two semiconductor chips are placed on a carrier. The at least two semiconductor chips are then covered with a molding material. An exposed portion of the at least two semiconductor chips is provided. A first layer of conductive material is applied over the exposed portion of the at least two semiconductor chips to electrically connect to a contact pad on the exposed portion of the at least two semiconductor chips. The at least two semiconductor chips are singulated.

Claims

1. A method of manufacturing a semiconductor device, comprising:

placing at least two semiconductor chips on a carrier;

covering the at least two semiconductor chips with molding material;

providing for an exposed portion of the at least two semiconductor chips;

applying a first layer of conductive material over the exposed portion of the at least two semiconductor chips, wherein the first layer of conductive material electrically connects to a contact pad on the exposed portion of the at least two semiconductor chips; and

singulating the at least two semiconductor chips.

2. The method of claim 1, wherein the exposed portion of the at least two semiconductor chips is provided by selectively removing a first portion of the molding material from the at least two semiconductor chips.

3. The method of claims 2, comprising performing selectively removing of the first portion of the molding material by at least one of mechanical drilling, laser drilling and etching.

4. The method of claim 1, further comprising:

selectively removing a second portion of the molding material from the carrier to selectively expose a portion of the carrier.

5. The method of claims 4, comprising performing selectively removing the second portion of the molding material by at least one of mechanical drilling, laser drilling and etching.

6. The method of claim 4, further comprising:

covering the selectively exposed portion of the carrier with the conductive material of the first layer.

7. The method of claim 1, comprising applying the conductive material of the first layer by a deposition process.

8. The method of claim 1, comprising applying the conductive material of the first layer by attaching a metal sheet to the contact pad.

9. The method of claim 1, further comprising:

generating the contact pad after providing for an exposed portion of the at least two semiconductor chips.

10. A method of manufacturing a semiconductor device, comprising:

placing at least two semiconductor chips on a carrier;

covering the at least two semiconductor chips with molding material;

providing for an exposed portion of the at least two semiconductor chips;

applying a first layer of conductive material over the exposed portion of the at least two semiconductor chips, wherein the first layer of conductive material electrically connects to a contact pad on the exposed portion of the at least two semiconductor chips; and

removing the at least two semiconductor chips from the carrier.

11. The method of claim 10, further comprising:

depositing a second layer of conductive material over a main surface of the at least two semiconductor chips which has been released from the carrier.

12. The method of claim 11, further comprising:

structuring the second layer of conductive material to form external terminals of the module.

13. A module, comprising:

a semiconductor chip having a first main chip surface, a second main chip surface and a contact pad on the first main chip surface;

a molding material accommodating the semiconductor chip, the molding material having a first mold surface, a second mold surface and a channel which opens to the first mold surface and the second mold surface;

a first layer of conductive material applied over the first main chip surface and the first mold surface, the first layer of conductive material being electrically connected to the contact pad; and

a conductive element being electrically connected to the first layer of conductive material and extending through the channel.

14. The module of claim 13, comprising wherein the molding material is made of an epoxy material.

15. The module of claim 13, further comprising:

at least one further contact pad on the second main chip surface.

16. The module of claim 13, comprising wherein the first layer of conductive material is greater in thickness than 10 μ

m, in particular 50 μ

m.

17. The module of claim 13, comprising wherein the first layer of conductive material is a deposited metal layer.

18. The module of claim 17, comprising wherein the conductive element is an integral part of the first layer made of deposited metal.

19. The module of claim 13, comprising wherein the first layer of conductive material is a metal sheet.

20. The module of claim 13, comprising wherein the conductive element is made of a solder material.

21. The module of claim 13, further comprising:

a second layer of conductive material applied over the second main chip surface.

22. The module of claim 21, comprising wherein the second layer of conductive material is structured to form external terminals of the module.

23. A module, comprising:

a semiconductor chip having a first main chip surface, a second main chip surface, a first contact pad on the first main chip surface and a second contact pad on the second main chip surface;

a molding material accommodating the semiconductor chip, the molding material having a first mold surface and a second mold surface;

a first layer of conductive material applied over the first main chip surface and the first mold surface, the layer of conductive material being electrically connected to the first contact pad; and

a second layer of conductive material applied over the second main chip surface and the second mold surface, the second layer of conductive material being electrically connected to the second contact pad.

24. The module of claim 23, comprising wherein the second layer of conductive material is structured to form external terminals of the module.

25. A module, comprising:

a semiconductor chip having a first main chip surface, a second main chip surface and a contact pad on the first main chip surface;

a molding material accommodating the semiconductor chip, the molding material having a first mold surface, a second mold surface and a channel which opens to the first mold surface and the second mold surface;

means for providing a first layer of conductive material applied over the first main chip surface and the first mold surface, the first layer means being electrically connected to the contact pad; and

a conductive element being electrically connected to the first layer means and extending through the channel.