HEAT SINK STRUCTURE AND SEMICONDUCTOR PACKAGE AS WELL AS METHOD FOR CONFIGURING HEAT SINKS ON A SEMICONDUCTOR PACKAGE

• US 20090230544A1
• Filed: 06/09/2008
• Published: 09/17/2009
• Est. Priority Date: 03/11/2008
• Status: Abandoned Application

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: LEE, Chang Chi, WANG, Tong Hong
• Application Number:
  US12/135,554
• Publication Number:
  US 20090230544A1
• Time in Patent Office: Days
• US Class Current: 257/712
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/3736 Metallic materials H01L23/3732, H01L23/3733, H01L23/3735, H01L23/3737, H01L23/3738 take precedence
• CPC Class Codes: H01L 23/42 Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16195 Flat cap [not enclosing an internal cavity]

Abstract

A heat sink structure according to the present invention is provided. The heat sink has a through opening extending from the upper surface through to the lower surface. A solder is disposed in the through opening and on the upper and lower surfaces of the heat sink, wherein the portion of the solder in the through opening is connected with the portions of the solder on the upper and lower surfaces.

Claims

1. A heat sink structure, comprising:

a heat sink having a first surface, a second surface opposing to the first surface and a through opening extending from the first surface through to the second surface; and

a solder disposed in the through opening and on the second surface of the heat sink, wherein the portion of the solder in the through opening is connected with the portion of the solder on the second surface.

2. The heat sink structure as claimed in claim 1, wherein the solder is further disposed on the first surface of the heat sink and the portion of the solder in the through opening is connected with the portion of the solder on the first surface.

3. The heat sink structure as claimed in claim 2, wherein the solder is disposed on substantially full of the first surface of the heat sink.

4. The heat sink structure as claimed in claim 2, further comprising:

a gold layer coated on the heat sink and in contact with the solder.

5. The heat sink structure as claimed in claim 2, further comprising:

a nickel/gold layer coated on the heat sink and in contact with the solder.

6. The heat sink structure as claimed in claim 2, wherein the solder is made of indium or alloys thereof.

7. A method for configuring heat sinks on a semiconductor package, comprising the steps of:

providing a substrate, the substrate having upper and lower surfaces;

disposing a chip on the upper surface of the substrate;

providing a first heat sink, the first heat sink having upper and lower surfaces, wherein the upper and lower surfaces of the first heat sink are pre-applied with a solder;

disposing the first heat sink on the chip;

disposing a second heat sink on the first heat sink; and

performing a reflow process to have the portions of the solder on the upper and lower surfaces of the first heat sink affixed to the second heat sink and the chip, respectively.

8. The method as claimed in claim 7, further comprising:

disposing a ring between the upper surface of the substrate and the lower surface of the first heat sink, the ring surrounding the chip.

9. The method as claimed in claim 7, wherein the first heat sink further comprises a through opening extending from the upper surface through to the lower surface, the solder is further disposed in the through opening and the portion of the solder in the through opening is connected with the portions of the solder on the upper and lower surfaces of the first heat sink.

10. The method as claimed in claim 7, wherein the solder is made of indium or alloys thereof.

11. The method as claimed in claim 7, wherein the chip has an active surface, the active surface of the chip is faced down on the upper surface of the substrate, the method further comprises:

disposing a plurality of first solder balls on the active surface of the chip and electrically connecting the first solder balls to the upper surface of the substrate; and

covering the first solder balls with an underfill encapsulant.

12. The method as claimed in claim 11, further comprising:

disposing a plurality of second solder balls on the lower surface of the substrate.

13. A semiconductor package, comprising:

a substrate having upper and lower surfaces;

a chip disposed on the upper surface of the substrate;

a first heat sink disposed on the chip, having an upper surface, a lower surface and a through opening extending from the upper surface through to the lower surface; and

a solder affixed in the through opening of the first heat sink and between the chip and first heat sink.

14. The semiconductor package as claimed in claim 13, further comprising:

a second heat sink disposed on the first heat sink,

wherein the solder is further affixed between the first and second heat sinks and is connected with the portion of the solder in the through opening.

15. The semiconductor package as claimed in claim 13, further comprising:

a ring disposed between the upper surface of the substrate and the lower surface of the first heat sink, the ring surrounding the chip.

16. The semiconductor package as claimed in claim 13, wherein the solder is made of indium or alloys thereof.

17. The semiconductor package as claimed in claim 13, wherein the chip has an active surface, the active surface of the chip is faced down on the upper surface of the substrate, the semiconductor package further comprises:

a plurality of first solder balls disposed on the active surface of the chip and electrically connected to the upper surface of the substrate; and

an underfill encapsulant covering the first solder balls.

18. The semiconductor package as claimed in claim 13, further comprising:

a plurality of second solder balls disposed on the lower surface of the substrate.