METHOD OF POST-MOLD GRINDING A SEMICONDUCTOR PACKAGE

• US 20090230567A1
• Filed: 03/11/2008
• Published: 09/17/2009
• Est. Priority Date: 03/11/2008
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kiong, James Yii Lee, Boon Hooi, Max Mah, Phing, Tang Shiau, Tan, Chong Hin, Sahadevan, Shivaram
• Granted Patent: US 8,124,471 B2
• Time in Patent Office: Days
• US Class Current: 257/783
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68386 Separation by peeling
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01084 Polonium [Po]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18161 of a flip chip
• CPC Class Codes: Y10S 438/959 Mechanical polishing of wafer

Abstract

A method of grinding a molded semiconductor package to a desired ultra thin thickness without damage to the package is disclosed. Prior to grinding a molded package to a desired package thickness, the package may be protected from excessive mechanical stress generated during grinding by applying a protective tape to enclose interconnects formed on the package. This way, the protective tape provides support to the semiconductor package during package grinding involving the mold material as well as the die. In the post-grind package, the grinded die surface may be exposed and substantially flush with the mold material. The protective tape may then be removed to prepare the post-grind package for connection with an external device or PCB.

Claims

1. A method comprising:

providing a molded semiconductor package having a die attached to a substrate;

providing a plurality of interconnects on a substrate surface distant from the die;

applying a protective tape to the substrate surface to form a substantially even arrangement enclosing the plurality of interconnects;

grinding the molded package to reduce the package thickness, including

grinding a mold material and a die surface distant from the substrate, wherein the die surface is exposed and substantially flush with the mold material after grinding; and

removing the protective tape from the substrate.

2. The method according to claim 1, wherein the protective tape includes a pliable layer to conform around the plurality of interconnects and a backing layer to provide rigid support to the pliable layer.

3. The method according to claim 2, wherein applying the protective tape includes roller-pressing the protective tape against the substrate surface.

4. The method according to claim 2, wherein removing the protective tape from the substrate includes heating a portion of the protective tape to loosen the portion of the protective tape.

5. The method according to claim 2, wherein the pliable layer includes a light-curable material.

6. The method according to claim 5, wherein removing the protective tape from the substrate includes curing the pliable layer of the protective layer by a light radiation to decrease an adhesive property of the pliable layer.

7. The method according to claim 2, wherein grinding the molded package includes grinding a portion of the mold material encapsulating the die prior to grinding the die surface.

8. The method according to claim 7, wherein grinding the portion of the mold material and grinding the die surface are performed at different speeds.

9. The method according to claim 1, wherein grinding the molded package is to reduce the thickness of the die to between 50 microns to 200 microns.

10. The method according to claim 1, wherein grinding the molded package is to reduce the thickness of the package to between 500 microns to 1 millimeter.

11. The method according to claim 1, wherein the molded semiconductor package includes an underfill material interposed between the die and the substrate.

12. A package comprising:

a die attached to a substrate;

a plurality of interconnects provided on a substrate surface distant from the die;

a mold material at least partially encapsulating the die; and

a protective tape applied on the substrate to form a substantially even arrangement enclosing the plurality of interconnects to provide mechanical stress support to the plurality of interconnects during grinding, wherein the protective tape is to be removed after grinding.

13. The package according to claim 12, wherein the protective tape includes a pliable layer to conform around the plurality of interconnects and a backing layer to provide rigid support to the pliable layer.

14. The package according to claim 13, wherein the pliable layer includes a light-curable material.

15. The package according to claim 12, further comprising an underfill material interposed between the die and the substrate.