Magnetoresistive Tunnel Junction Magnetic Device and Its Application to MRAM

• US 20090231909A1
• Filed: 10/13/2006
• Published: 09/17/2009
• Est. Priority Date: 10/14/2005
• Status: Active Grant

• Current Assignee: Commissariat a L'Energie Atomique (AES Corporation), Centre National De La Recherche Scientifique
• Original Assignee: Commissariat a L'Energie Atomique (AES Corporation), Centre National De La Recherche Scientifique
• Inventors: Faure-Vincent, Jerome, Dieny, Bernard, Samson, Yves, Warin, Patrick, Vedyaev, Anatoly, Jamet, Matthieu
• Granted Patent: US 7,821,818 B2
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: B82Y 25/00 Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: H01F 10/3254 the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ]
• CPC Class Codes: H01F 10/3286 Spin-exchange coupled multilayers having at least one layer with perpendicular magnetic anisotropy
• CPC Class Codes: H01F 41/305 applying the spacer or adjusting its interface, e.g. in order to enable particular effect different from exchange coupling
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10N 50/10 Magnetoresistive devices

Abstract

The magnetic device comprises a magnetic device comprising a magnetoresistive tunnel junction (100), itself comprising: a reference magnetic layer (120) having magnetization in a direction that is fixed; a storage magnetic layer (110) having magnetization in a direction that is variable; and an intermediate layer (130) acting as a tunnel barrier that is essentially semiconductor or electrically insulating and that separates the reference magnetic layer (120) from the storage magnetic layer (110). The potential profile of the intermediate layer (130) is asymmetrical across the thickness of said layer (130) so as to produce a current response that is asymmetrical as a function of the applied voltage. The device is applicable to magnetic random access memories.

Claims

1. A magnetic device comprising a magnetoresistive tunnel junction, itself comprising:

a reference magnetic layer having magnetization in a direction that is fixed;

a storage magnetic layer having magnetization in a direction that is variable; and

an intermediate layer acting as a tunnel barrier that is essentially semiconductor or electrically insulating and that separates the reference magnetic layer from the storage magnetic layer;

the device being characterized in that the potential profile of the intermediate layer is asymmetrical across the thickness of said layer so as to produce a current response that is asymmetrical as a function of the applied voltage.

2. A device according to claim 1, characterized in that the intermediate layer acting as a tunnel barrier includes in its thickness, at a first distance (e₁) from the storage magnetic layer and at a second distance (e₂) from the reference magnetic layer, a very thin layer of a metallic or semiconductive material other than that or those constituting the remainder of the intermediate layer so as to create a potential well that is localized and asymmetrical within the tunnel barrier.

3. A device according to claim 2, characterized in that said very thin layer presents a thickness of one to two planes of atoms.

4. A device according to claim 1, characterized in that said very thin layer presents a thickness of a fraction of a plane of atoms.

5. A device according to claim 2, characterized in that the second distance (e₂) presents a value that is different from that of the first distance (e₁).

6. A device according to claim 2, characterized in that the remainder of the intermediate layer comprises different insulating or semiconductive materials on either side of the very thin layer.

7. A device according to claim 1, characterized in that said intermediate layer acting as a tunnel barrier includes a doped region within its thickness at a first distance (e₁) from the storage magnetic layer and at a second distance (e₂) from the reference magnetic layer, where the second distance presents a value different from that of the first distance (d₁), the doped region being doped by inserting a material other than that constituting the remainder of the intermediate layer so as to create in the doped region a potential well that is localized and asymmetrical within the tunnel barrier.

8. A device according to claim 7, characterized in that one of the first and second distances (e₁, e₂) is zero such that the doped region is in contact with one of the two outer interfaces of said intermediate layer with the reference magnetic layer and with the storage magnetic layer.

9. A device according to claim 1, characterized in that said intermediate layer acting as a tunnel barrier comprises a stack of at least a first layer of a first insulating or semiconductive material and presenting a first thickness (e₁, e₂), and of at least one second layer of a second insulating or semiconductive material different from said first material and presenting a second thickness (e₂).

10. A device according to claim 9, characterized in that the second thickness (e₂) presents a value different from the first thickness (e₁).

11. A device according to claim 1, characterized in that said very thin layer is made of a material selected from aluminum, gold, silver, silicon, and germanium and said intermediate layer comprises alumina.

12. A device according to claim 2, characterized in that said very thin layer is made of a material selected from aluminum, gold, silver, silicon, and germanium.

13. A device according to claim 1, characterized in that said intermediate layer comprises magnesium oxide.

14. A device according to claim 2, characterized in that said intermediate layer comprises magnesium oxide and that said very thin layer is made of a material selected from chromium, ruthenium, tantalum, gold, silver, silicon, and germanium.

15. A device according to claim 1, characterized in that the intermediate layer acting as a tunnel barrier presents a thickness lying in the range 1 nm to 3 nm.

16. A device according to claim 7, characterized in that the intermediate layer acting as a tunnel barrier presents thickness lying in the range 2 nm to 3 nm, and in that the doped region presents thickness lying in the range 0.5 nm to 1 nm.

17. A device according to claim 7, characterized in that the intermediate layer is made of alumina or of magnesium oxide, and in that the doped region comprises metallic or semiconductor doping elements comprising at least one of the materials constituted by aluminum, gold, silver, chromium, ruthenium, tantalum, and silicon.

18. A memory comprising an array of memory cells addressable by a set of bit lines and of word lines, said memory being characterized in that each memory cell comprises a magnetic device according to claim 1, and in that each magnetic device is connected to one bit line and to one word line without interposing any additional switch element.

19. A memory according to claim 18, characterized in that it comprises N*N memory cells distributed in a two-dimensional architecture, where N is an integer, each bit line serving N memory cells, and each word line serving N memory cells.

20. A memory according to claim 18, characterized in that it presents three-dimensional architecture comprising a set of P superposed layers, each of N*N memory cells, each connected to one bit line and to one word line, where P and N are integers, and in that each bit line and each word line serving memory cells other than the memory cells of the outer layers is associated with memory cells belonging to two different adjacent layers (P_i, P_i+1).

21. A memory according to claim 18, characterized in that it presents three-dimensional architecture comprising a stack of P superposed layers of N*N memory cells, memory cells of each layer (P_i, P_i+1) being distributed in a two-dimensional architecture, P and N being integers, each bit line serving N memory cells and each word line serving N memory cells within one two-dimensional architecture layer, and in that an insulating separator layer is interposed between two successive two-dimensional architecture layers (P_i, P_i+1) in periodic manner in the stack of P superposed layers.

22. A device according to claim 8, characterized in that the intermediate layer acting as a tunnel barrier presents thickness lying in the range 2 nm to 3 nm, and in that the doped region presents thickness lying in the range 0.5 nm to 1 nm.

23. A device according to claim 8, characterized in that the intermediate layer is made of alumina or of magnesium oxide, and in that the doped region comprises metallic or semiconductor doping elements comprising at least one of the materials constituted by aluminum, gold, silver, chromium, ruthenium, tantalum, and silicon.

24. A device according to claim 16, characterized in that the intermediate layer is made of alumina or of magnesium oxide, and in that the doped region comprises metallic or semiconductor doping elements comprising at least one of the materials constituted by aluminum, gold, silver, chromium, ruthenium, tantalum, and silicon.

25. A device according to claim 3, characterized in that

the second distance (e₂) presents a value that is different from that of the first distance (e₁);

and

the remainder of the intermediate layer comprises different insulating or semiconductive materials on either side of the very thin layer.

26. A device according to claim 1, characterized in that

said intermediate layer comprises magnesium oxide;

said very thin layer is made of a material selected from chromium, ruthenium, tantalum, gold, silver, silicon, and germanium; and

the intermediate layer acting as a tunnel barrier presents a thickness lying in the range 1 nm to 3 nm.

27. A memory comprising an array of memory cells addressable by a set of bit lines and of word lines, said memory being characterized in that each memory cell comprises a magnetic device according to claim 7, and in that each magnetic device is connected to one bit line and to one word line without interposing any additional switch element;

the memory characterized in that

it comprises N*N memory cells distributed in a two-dimensional architecture, where N is an integer, each bit line serving N memory cells, and each word line serving N memory cells;

it presents three-dimensional architecture comprising a set of P superposed layers, each of N*N memory cells, each connected to one bit line and to one word line, where P and N are integers, and in that each bit line and each word line serving memory cells other than the memory cells of the outer layers is associated with memory cells belonging to two different adjacent layers (P_i, P_i+1); and

it presents three-dimensional architecture comprising a stack of P superposed layers of N*N memory cells, memory cells of each layer (P_i, P_i+1) being distributed in a two-dimensional architecture, P and N being integers, each bit line serving N memory cells and each word line serving N memory cells within one two-dimensional architecture layer, and in that an insulating separator layer is interposed between two successive two-dimensional architecture layers (P_i, P_i+1) in periodic manner in the stack of P superposed layers.

28. A memory comprising an array of memory cells addressable by a set of bit lines and of word lines, said memory being characterized in that each memory cell comprises a magnetic device according to claim 8, and in that each magnetic device is connected to one bit line and to one word line without interposing any additional switch element;

the memory characterized in that

it comprises N*N memory cells distributed in a two-dimensional architecture, where N is an integer, each bit line serving N memory cells, and each word line serving N memory cells;

it presents three-dimensional architecture comprising a set of P superposed layers, each of N*N memory cells, each connected to one bit line and to one word line, where P and N are integers, and in that each bit line and each word line serving memory cells other than the memory cells of the outer layers is associated with memory cells belonging to two different adjacent layers (P_i, P_i+1); and

it presents three-dimensional architecture comprising a stack of P superposed layers of N*N memory cells, memory cells of each layer (P_i, P_i+1) being distributed in a two-dimensional architecture, P and N being integers, each bit line serving N memory cells and each word line serving N memory cells within one two-dimensional architecture layer, and in that an insulating separator layer is interposed between two successive two-dimensional architecture layers (P_i, P_i+1) in periodic manner in the stack of P superposed layers.