NON-VOLATILE SEMICONDUCTOR MEMORY WITH PAGE ERASE

• US 20090231928A1
• Filed: 05/28/2009
• Published: 09/17/2009
• Est. Priority Date: 03/29/2006
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Kim, Jin-Ki
• Granted Patent: US 7,872,921 B2
• Time in Patent Office: Days
• US Class Current: 365/185.220
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

In a nonvolatile memory, less than a full block may be erased as one or more pages. A select voltage is applied through pass transistors to each of plural selected wordlines and an unselect voltage is applied through pass transistor to each of plural unselected wordlines of a selected block. A substrate voltage is applied to the substrate of the selected block. A common select voltage may be applied to each selected wordline and the common unselect voltage may be applied to each unselected wordline. Select and unselect voltages may be applied to any of the wordlines of a select block. A page erase verify operation may be applied to a block having plural erased pages and plural nonerased pages.

Claims

1. A method of verifying erase of selected one to m−

1 of m pages of memory cells within a selected block of a non-volatile memory array, the block having a plurality of strings of memory cells on a substrate and m word lines across the strings each operably connected to a respective one of the m pages of memory cells, the method comprising;

applying a select verify voltage to each word line corresponding to the selected one to m−

1 pages for causing each memory cell of the selected one to m−

1 pages to conduct only if erased;

applying an unselect verify voltage to each word line corresponding to unselected pages for causing each memory cell of the unselected pages to conduct regardless of a respective state of each memory cell of the unselected pages; and

sensing a state of each string for verifying erase of each memory cell of each selected word line.

2. The method as claimed in claim 1, wherein applying the select verify voltage comprises applying 0 Volts to each word line corresponding to the selected one to m−

1 pages.

3. The method as claimed in claim 1, wherein applying the unselect verify voltage comprises applying a read voltage to each word line corresponding to the unselected pages.

4. The method as claimed in claim 1, further comprising:

connecting each string to a common source line voltage; and

selecting a level of the common source line voltage from a plurality of voltage levels dependent on a number of the of selected word lines.

5. The method as claimed in claim 1, further comprising:

connecting each string to an common source line voltage; and

selecting a level of the common source line voltage from a plurality of voltage levels wherein a number of the plurality of voltage levels is substantially less than m−

1.

6. A nonvolatile memory including a memory array having a plurality of blocks, each block comprising:

m pages of memory cells,

a plurality of strings of memory cells on a substrate,

m word lines across the strings each operably connected to a respective one of the m pages,

a word line decoder for applying;

a select verify voltage to each word line of a plurality of erased pages in the block if the block is selected; and

an unselect verify voltage to each word line of a plurality of non-erased pages in the block if the block is selected, and

sensors for sensing states of the strings.

7. A nonvolatile memory as claimed in claim 6, wherein each string is connectable to a common source line voltage, a level of the common source line voltage being selectable from one of a plurality of voltage levels dependent on a number of the plurality of erased pages.

8. A nonvolatile memory as claimed in claim 7, wherein the level of the common source line voltage is selected to be substantially within a range of r=0.3 to 0.5 Volts if the number of the plurality of erased pages is 1.

9. A nonvolatile memory as claimed in claim 8, wherein the selected level of the common source line voltage is reduced by r/m for each additional erased page.

10. A nonvolatile memory as claimed in claim 8, wherein the selected level of the common source line voltage is reduced as the number of the plurality of erased pages increases.

11. A method of verifying erase of one or more pages in a non-volatile memory array having plural strings of memory cells on the substrate and word lines across the strings to pages of memory cells, the method comprising:

to each of plural selected word lines of a selected block, applying a select verify voltage that causes each memory cell to conduct only if erased;

to each of plural unselected word lines of the selected block, applying an unselect verify voltage that causes each memory cell to conduct regardless of state; and

sensing state of each string to verify erase of each memory cell of each selected word line.

12. A method as recited in claim 11 wherein each string is connected to an end voltage, the level of the end voltage being selected from one of plural voltage levels dependent on the number of selected word lines.

13. A nonvolatile memory comprising:

a memory array comprising plural strings of memory cells on a substrate and word lines across the strings to pages of memory cells;

a word line decoder that applies a select verify voltage to each word line of plural erased pages in a selected block and an unselect verify voltage to each word line of plural non-erased pages in the selected block; and

sensors that sense state of strings of the selected block.

14. A nonvolatile memory as claimed in claim 13 wherein each string is connected to an end voltage, the level of the end voltage being selected from one of plural voltage levels dependent on the number of selected word lines.