METHOD AND APPARATUS FOR PROCESSING FAILURES DURING SEMICONDUCTOR DEVICE TESTING

• US 20090235131A1
• Filed: 03/11/2008
• Published: 09/17/2009
• Est. Priority Date: 03/11/2008
• Status: Active Grant

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Kemmerling, Todd Ryland
• Granted Patent: US 8,122,309 B2
• Time in Patent Office: Days
• US Class Current: 714/723
• CPC Class Codes: G06F 11/273 Tester hardware, i.e. output processing circuits G06F11/263 takes precedence
• CPC Class Codes: G11C 2029/5606 Error catch memory
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

Methods and apparatus for processing failures during semiconductor device testing are described. Examples of the invention can relate to testing a device under test (DUT). Fail capture logic can be provided, coupled to test probes and memory, to indicate only first failures of failures detected on output pins of the DUT during a test for storage in the memory.

Claims

1. Apparatus for testing a device under test (DUT), comprising:

fail capture logic, coupled to test probes and memory, to indicate only first failures of failures detected on output pins of the DUT during a test for storage in the memory.

2. The apparatus of claim 1, wherein the fail capture logic includes detection logic and disable logic, wherein the apparatus includes control logic, and wherein:

the detection logic is configured to indicate the failures on the output pins of the DUT;

the control logic is configured to store failure indications in the memory; and

the disable logic is configured to provide indications of the first failures to the control logic and block indications of the failures other than the first failures from the control logic during the test.

3. The apparatus of claim 2, wherein the disable logic includes a logic circuit for each of the output pins, the logic circuit including combinatorial logic and a flip-flop.

4. The apparatus of claim 2, further comprising:

analog-to-digital converter (ADC) logic coupled between the test probes and the fail capture logic, the ADC logic configured to sample voltages of test result signals, the test result signals derived from output signals of the output pins.

5. The apparatus of claim 4, wherein the ADC logic is configured to generate codes in response to the sampled voltages and to provide the codes to the detection logic, and wherein the detection logic is configured to indicate the failures in response to the codes.

6. The apparatus of claim 5, wherein the detection logic compares the codes to expected codes to indicate the failures.

7. The apparatus of claim 1, wherein the DUT includes multiple devices each having a portion of the output pins.

8. A test assembly, comprising:

a probe card assembly having test probes configured to contact pins of a device under test (DUT);

test instruments having test channels coupled to a memory, each of the test channels including;

fail capture logic, coupled to at least one of the test probes contacting at least one output pin of the pins, to indicate only first failures on the at least one output pin during a test for storage in the memory.

9. The test assembly of claim 8, wherein the fail capture logic includes detection logic and disable logic, wherein the test instruments include control logic, and wherein

the detection logic is configured to indicate the failures on the at least one output pin;

the control logic is configured to store failure indications in the memory; and

the disable logic is configured to provide indications of the first failures to the control logic and block indications of the failures other than the first failures from the control logic during the test.

10. The test assembly of claim 9, wherein the disable logic includes a logic circuit for each of the output pins, the logic circuit including:

a flip-flop including a set input coupled to the detection logic and an inverted output; and

a logic gate having a first input coupled to the detection logic, a second input coupled to the inverted output of the flip-flop, and an output coupled to the control logic.

11. The test assembly of claim 10, wherein the flip-flop includes a reset input and the test assembly comprises:

a register coupled to the reset input.

12. The test assembly of claim 9, wherein each of the test channels further includes:

an analog-to-digital converter (ADC) coupled between the fail capture logic and the at least one output pin, the ADC configured to obtain at least one sample of a voltage of a test result signal, the test result signal being derived from an output signal of each of the at least one output pin.

13. The test assembly of claim 12, wherein the ADC is configured to generate at least one code in response to the at least one sample and to provide the at least one code to the detection logic, and wherein the detection logic is configured to indicate the failures in response to the at least one code.

14. The test assembly of claim 13, wherein the detection logic is configured to compare the at least one code to at least one expected code to indicate the failures.

15. The test assembly of claim 8, wherein the DUT includes multiple devices each having a portion of the output pins.

16. A method of testing a device under test (DUT) using a probe card assembly, comprising:

applying test signals to input pins of the DUT during a test via test probes supported on the probe card assembly;

receiving test result signals derived from output pins of the DUT responsive to the test signals; and

storing in a memory only indications of first failures on the output pins as identified based on the test result signals for the test.

17. The method of claim 16, wherein the step of receiving comprises:

sampling voltages of the test result signals to generate codes.

18. The method of claim 17, further comprising:

comparing the codes with expected codes to indicate failures on the output pins.

19. The method of claim 18, wherein the step of storing comprises:

blocking indications of the failures other than the first failures on the output pins from storage in the memory.

20. The method of claim 16, wherein the DUT includes multiple devices each having a portion of the output pins.

21-40. -40. (canceled)