Variable Performance Ranking and Modification in Design for Manufacturability of Circuits

• US 20090235214A1
• Filed: 03/11/2008
• Published: 09/17/2009
• Est. Priority Date: 03/11/2008
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Baker, Faye D., Levy, Mark D., Beckenbaugh, Mark R., Freerksen, Jason J.
• Granted Patent: US 7,823,106 B2
• Time in Patent Office: Days
• US Class Current: 716/100
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A method, computer system and program product introduce adding a variable performance ranking parameter to a diagram of a circuit to drive implementation of modifications that are yield improving, performance boosting, or performance-neutral. The information is paired to accomplish a more complete design for manufacturability modification in the design of circuits implemented on chips. In this matter, both yield and chip performance are improved.

Claims

1. A method of designing a circuit by using design for manufacturability (DFM) tools, comprising:

generating a diagram of a circuit design;

applying a variable performance ranking parameter to said diagram and generating a grading for components of said circuit design; and

modifying the diagram of said circuit design based on said grading.

2. The method of claim 1, wherein said applying of a variable performance ranking parameter comprises assigning a criticality value from a plurality of criticality values to components of said circuit design.

3. The method of claim 2, wherein said plurality of criticality values comprise a range of values from a performance critical value to a non-critical value.

4. The method of claim 3, wherein full DFM rules are applied for a circuit design for all components assigned a non-critical value.

5. The method of claim 1, wherein modifications to said circuit design are selected for improving yield during manufacturing without degrading performance of manufactured circuits.

6. The method of claim 1, wherein said diagram of said circuit is generated using a predetermined set of ground rules for determining placement of components in said circuit, and further comprising modifying placement of components in said circuit, when two or more rules are in conflict, in a manner not detrimental to circuit performance and increasing of yield during manufacturing.

7. The method of claim 6, wherein placement of non-critical components is adjusted to increase yield during manufacturing.

8. The method of claim 1, wherein said modification of the circuit design comprises adjusting placement of non-critical components to increase yield during manufacturing.

9. The method of claim 6, wherein placement of critical components is adjusted to increase performance of the circuit.

10. The method of claim 1, wherein said modification of the circuit design comprises adjusting placement of critical components to increase performance of the circuit.

11. A computer system for designing a circuit by using design for manufacturing (DFM) tools, comprising:

first code for generating a diagram of a circuit design;

second code for applying a variable performance ranking parameter to said diagram and for generating a grading for components of said circuit design; and

third code for modifying the diagram of the circuit design based on said grading.

12. The system of claim 11, wherein said variable performance ranking parameter comprises a plurality of criticality values to be assigned to components of the circuit.

13. The system of claim 12, wherein said plurality of criticality values comprises a range of values from a performance critical value to a performance non-critical value.

14. The system of claim 12, further comprising a database of DFM rules for designing a circuit diagram, and wherein said third code is configured for applying full DFM rules for all components assigned a non-critical value.

15. The system of claim 11, wherein said third code is configured for modifying the circuit design diagram to improve during manufacturing without degrading performance of manufactured circuits.

16. The system of claim 11, further comprising a database of ground rules for determining placement of said circuit components, and said third code being configured for modifying placement of a component in said circuit when two or more rules are in conflict, in a manner not detrimental to circuit performance and to increase yield during manufacturing.

17. The system of claim 16, wherein said third code is further configured for conducting said modification to adjust placement of non-critical components to increase yield during manufacturing.

18. The system of claim 16, wherein said third code is further configured for conducting said modification to adjust placement of critical components to increase performance of the circuit.

19. The system of claim 11, wherein said third code is further configured for conducting said modification to adjust placement of non-critical components to increase yield during manufacturing and to adjust placement of critical components to increase performance of the circuit.

20. A program product, comprising:

storage medium; and

first code on said storage medium configured for generating a diagram of a circuit design according to design for manufacturing (DFM) rules, second code for applying a variable ranking parameter to said diagram for generating a grading for components of said circuit design, and third code for modifying the diagram of the circuit design based on said grading.