Enhanced Control of CPU Parking and Thread Rescheduling for Maximizing the Benefits of Low-Power State

• US 20090235260A1
• Filed: 12/12/2008
• Published: 09/17/2009
• Est. Priority Date: 03/11/2008
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Rystsov, Denis, Steinman, Maurice B., Branover, Alexander
• Granted Patent: US 8,112,648 B2
• Time in Patent Office: Days
• US Class Current: 718/102
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 2209/508 Monitor
• CPC Class Codes: G06F 9/5027 the resource being a machine, e.g. CPUs, Servers, Terminals
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system may comprise a plurality of processing units and a scheduler configured to maintain a record for each respective processing unit. Each respective record may comprise entries which may indicate 1) how long the respective processing unit has been residing in an idle state, 2) a present power-state in which the respective processing unit resides, and 3) whether the respective processing unit is a designated default (bootstrap) processing unit. The scheduler may select one or more of the plurality of processing units according to their respective records, and assign impending instructions to be executed on the selected one or more processing units. Where additional processing units are required, the scheduler may also insert an instruction to trigger an inter-processor interrupt to transition one or more processing units out of idle-state. The scheduler may then assign some impending instructions to these one or more processing units.

Claims

1. A method for scheduling tasks to execute on a plurality of processing units, the method comprising:

determining whether any of the plurality of processing units are available for executing scheduled tasks;

in response to determining that at least one of the plurality of processing units is available for executing the scheduled tasks, assigning the scheduled tasks to execute on the at least one of the plurality of processing units;

determining whether additional processing units are required for executing the scheduled tasks;

in response to determining that additional processing units are required for executing the scheduled tasks, executing an instruction to trigger an inter-processor interrupt;

in response to the inter-processor interrupt, waking up selected one or more of remaining ones of the plurality of processing units; and

assigning the scheduled tasks to also execute on the selected one or more of the remaining ones of the plurality of processing units.

2. The method of claim 1, wherein said waking up comprises updating a table to indicate that the one or more of the remaining ones of the plurality of processing units are available for executing the scheduled tasks.

3. The method of claim 1, wherein said determining comprises performing a lookup of a table, wherein the table comprises entries indicative of which of the plurality of processing units are available for executing the scheduled tasks.

4. The method of claim 1, further comprising:

in response to determining that none of the plurality of processing units are available for executing the scheduled tasks, waking up a specified one of the plurality of processing units marked as a default processing unit.

5. The method of claim 4, further comprising the default processing unit determining whether any additional ones of the plurality of processing units are required, and in response to determining that additional ones of the plurality of processing units are required, waking up one or more additional ones of the plurality of processing units.

6. A system comprising:

a plurality of processing units configured to execute computer instructions; and

a memory element configured to store a table comprising;

a respective first entry for each respective processing unit of at least a subset of the plurality of processing units, wherein the first entry is indicative of how long the respective processing unit has been residing in an idle state;

wherein the system is configured to check the respective first entries in the table to identify which of the at least a subset of the plurality of processing units do not reside in an idle state;

wherein the system is further configured to assign impending computer instructions to execute on one or more of the at least a subset of the plurality of processing units identified as not residing in an idle state when the respective first entries in the table are checked.

7. The system of claim 6, wherein the table further comprises one or more of:

a respective second entry for each respective processing unit of the at least a subset of the plurality of processing units, wherein the second entry is indicative of a power-state in which the respective processing unit presently resides;

or

a respective third entry for each respective processing unit of the at least a subset of the plurality of processing units, wherein the third entry is indicative of whether the respective processing unit is a designated default (bootstrap) processing unit;

wherein the system is configured to transition the bootstrap processing unit out of idle state first, when all of the at least a subset of the plurality of processing units are in an idle state.

8. The system of claim 7, wherein the bootstrap processing unit is configured to determine whether to transition out of idle state any other ones of the at least a subset of the plurality of processing units that presently reside in an idle state.

9. The system of claim 7, wherein in assigning the impending computer instructions to execute on the one or more of the at least a subset of the plurality of processing units identified as not residing in an idle state, the system is configured to check the respective second entries in the table and select the one or more of the at least a subset of the plurality of processing units according to the respective power-states in which the at least a subset of the plurality of processing units presently reside.

10. A system comprising:

a plurality of processing units configured to execute computer instructions; and

a scheduler configured to maintain a table for tracking and managing idle-state residency of each respective processing unit of the plurality of processing units, wherein the table comprises;

a respective first entry for each respective processing unit, wherein the first entry is indicative of how long the respective processing unit has been residing in an idle state;

a respective second entry for each respective processing unit, wherein the second entry is indicative of a power-state in which the respective processing unit presently resides; and

a respective third entry for each respective processing unit, wherein the third entry is indicative of whether the respective processing unit is a designated default (bootstrap) processing unit.

11. The system of claim 10, wherein the scheduler is further configured to:

check the table to identify which of the plurality of processing units do not presently reside in an idle state and are therefore available for executing impending instructions; and

assign at least a first portion of the impending instructions to execute on one or more processing units identified as not being in an idle state.

12. The system of claim 11, wherein the scheduler is further configured to:

check the table to identify bootstrap processing units; and

transition the bootstrap processing units out of idle state first, when none of the plurality of processing units have been identified as being available for executing the impending instructions.

13. The system of claim 11, wherein the scheduler is further configured to:

determine whether additional processing units are required for executing the impending instructions, in addition to the one or more processing units identified as not being in an idle state; and

in response to determining that additional processing units are required, insert an instruction into the at least first portion of the impending instructions to trigger an inter-processor interrupt to transition selected processing units identified as being in an idle state, out of idle state.

14. The system of claim 13, wherein the scheduler is further configured to:

update the respective first and second entries for the selected processing units to reflect that the selected processing units are no longer in an idle state, and to indicate a respective present power-state of each of the selected processing units.

15. The system of claim 10, wherein the scheduler is comprised in one or more of:

an operating system executing on the system;

a high-level software program executing on the system;

a dedicated hardware module;

or

one or more system hardware components having a primary function different from the scheduler.

16. The system of claim 10, wherein the plurality of processing units are processor cores comprised in a processor.

17. A method for tracking and managing idle-state residency of each respective processing unit of a plurality of processing units, the method comprising:

maintaining a respective record for each respective processing unit, wherein each respective record comprises;

first information indicative of a present power-state in which the respective processing unit resides;

second information indicative of whether the respective processing unit resides in an idle state; and

third information indicative of whether the respective processing unit is specified as a default (bootstrap) processing unit;

selecting one or more processing units of the plurality of processing units according to the respective records; and

assigning impending instructions to execute on the selected one or more processing units.

18. The method of claim 17, wherein said selecting comprises:

checking the second information in the respective records to determine whether any of the plurality of processing units are not residing in an idle-state, and are therefore available to execute the impeding instructions;

selecting the one or more processing units from processing units determined as not residing in an idle state.

19. The method of claim 18, further comprising:

determining whether additional processing units in addition to the selected one or more processing units are required for executing the impending instructions;

in response to said determining indicating that additional processing units are required, inserting an instruction into already executing impending instructions to trigger an inter-processor interrupt;

in response to the inter-processor interrupt, transitioning one or more processing units presently residing in an idle state out of idle-state; and

assigning at least a portion of the impending instructions to execute on the one or more processing units transitioned out of idle state.

20. The method of claim 19, further comprising updating the respective records to reflect a present power-state and idle-state residency of the plurality of processing units.