STACKED BIT LINE DUAL WORD LINE NONVOLATILE MEMORY

• US 20090236639A1
• Filed: 06/01/2009
• Published: 09/24/2009
• Est. Priority Date: 08/31/2005
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: LUNG, HSIANG-LAN
• Granted Patent: US 7,985,989 B2
• Time in Patent Office: Days
• US Class Current: 257/209
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics.

Claims

1. A memory device, comprising:

a substrate;

a polysilicon line substantially vertical to the substrate;

first and second conductive lines over the substrate;

a first memory cell between the first conductive line and the polysilicon line; and

a second memory cell between the second conductive line and the polysilicon line, wherein the first memory cell is over the second memory cell.

2. The memory device of claim 1, wherein the first and second conductive lines are arranged in respective first and second levels above the substrate.

3. The memory device of claim 1, wherein the first and second conductive lines comprise polysilicon having a conductivity type opposite that of the polysilicon line.

4. The memory device of claim 1, wherein the second conductive lines is directly above the first conductive line, and said first cell is disposed between the polysilicon line and the first conductive line, and the second memory cell is disposed between the polysilicon line and the second conductive line.

5. The memory device of claim 1, wherein said first and second memory cells comprise non-volatile memory cells.

6. The memory device of claim 1, wherein said first and second memory cells comprise anti-fuse elements.

7. A memory device, comprising:

a substrate;

a plurality of word lines and a plurality of bit lines over the substrate;

a plurality of plugs electrically coupled with the word lines;

a first memory cell disposed between one of the bit lines and one of the plugs; and

a second memory cell disposed between another one of the bit lines and another one of the plugs, wherein the first and second memory cells are not at the same level.

8. The memory device of claim 7, wherein the plurality of bit lines include a first set of bit lines and a second set of bit lines arranged in respective first and second levels above the substrate.

9. The memory device of claim 7, wherein the plurality of bit lines comprise polysilicon having a conductivity type opposite that of the plurality of plugs.

10. The memory device of claim 7, wherein the second set of bit lines is disposed directly above the first set of bit lines.

11. The memory device of claim 7, wherein said first and second memory cells comprise non-volatile memory cells.

12. The memory device of claim 7, wherein said first and second memory cells comprise anti-fuse elements.

13. A memory device, comprising:

a substrate;

first and second word lines over the substrate;

a first plug orthogonal to the first word line and the substrate;

a second plug orthogonal to the second word line and the substrate;

a first plurality of memory cells disposed on a first side wall beside the first plug; and

a second plurality of memory cells disposed on a second sidewall beside the second plug, wherein the first word line is over the second word line.

14. The memory device of claim 13, wherein said first and second memory cells comprise non-volatile memory cells.

15. The memory device of claim 13, wherein said first and second memory cells comprise anti-fuse elements.