IMPACT IONIZATION DEVICES AND METHODS OF MAKING THE SAME

• US 20090236657A1
• Filed: 03/24/2008
• Published: 09/24/2009
• Est. Priority Date: 03/24/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ananthan, Venkatesan
• Granted Patent: US 8,674,434 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7391 Gated diode structures
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

Impact ionization devices including vertical and recessed impact ionization metal oxide semiconductor field effect transistor (MOSFET) devices and methods of forming such devices are disclosed. The devices require lower threshold voltage than conventional MOSET devices while maintaining a footprint equal to or less than conventional MOSFET devices.

Claims

1. An impact ionization device, comprising:

a gate disposed in a trench in a substrate;

an insulating material disposed within the trench over the gate;

a drain region on a first side of the trench, at least a portion of the drain region disposed laterally adjacent the gate;

a source region on a second side of the trench laterally adjacent the insulating material, the drain region being N+ type or P+ type and the source region being N+ type or P+ type where the drain region is not the same type as the source region; and

,

an impact ionization region at least partially disposed between the source region and the gate.

2. The impact ionization device of claim 1, further comprising another insulating material separating both the gate and the insulating material from sidewalls of the trench.

3. The impact ionization device of claim 1, wherein a lower boundary of the source region is vertically separated from an upper surface of the gate by a distance.

4. The impact ionization device of claim 1, wherein the impact ionization region comprises a germanium material.

5. The impact ionization device of claim 1, wherein the gate is less than 100 nm wide.

6. An impact ionization device, the device comprising:

a pillar including a drain region disposed at a first end of the pillar and a source region disposed at a second end of the pillar, the source region being N+ type or P+ type and the drain region being N+ type or P+ type where the source region is not the same type as the drain region;

a gate disposed adjacent at least a portion of the pillar, at least a portion of the gate disposed laterally adjacent the drain region; and

an impact ionization region of the pillar at least partially disposed between the source region and the gate.

7. The impact ionization device of claim 6, wherein one of the drain region and the source region is an N+ doped region and the other of the drain region and the source region is a P+ doped region.

8. The impact ionization device of claim 6, further comprising an insulating material between the gate and the pillar.

9. The impact ionization device of claim 8, wherein the gate surrounds at least a portion of the pillar.

10. A method of forming an impact ionization device, the method comprising:

forming a gate dielectric material in a trench in a substrate;

depositing gate material within the trench;

depositing an insulating material within the trench over the gate material;

doping a first region of the substrate on a first side of the trench with a P-type dopant; and

doping a second region of the substrate on a second side of the trench with an N-type dopant such that the N-type dopant extends farther into the substrate than the P-type dopant.

11. The method of claim 10, wherein forming a gate dielectric material comprises:

forming an impact ionization material having an impact ionization rate greater than silicon on the substrate;

etching a trench in the impact ionization material and substrate; and

forming the gate dielectric material over the impact ionization material and within the trench.

12. The method of claim 11, wherein the P-type dopant is exclusively within the impact ionization material.

13. The method of claim 10, wherein forming a gate dielectric material within a trench comprises forming a gate dielectric material within a trench having a depth of approximately 1,000 Å

.

14. The method of claim 10, wherein depositing gate material within the trench further comprises planarizing the gate material such that an upper surface of the gate material is substantially planar with an upper surface of the substrate.

15. The method of claim 10, wherein forming a gate dielectric material in a trench in a substrate comprises forming a gate dielectric material in a trench in a substrate having a buried oxide therein.

16. The method of claim 10, further comprising:

applying a first mask prior to doping the first side of the trench with a P-type dopant;

removing the first mask; and

applying a second mask prior to doping the second side of the trench with an N-type dopant.

17. A method of forming an impact ionization device, the method comprising:

doping a substrate with an N-type dopant to form a drain region;

doping the substrate with a P-type dopant to form a source region;

etching the substrate to form a pillar comprising the drain region and the source region;

forming a gate adjacent at least a portion of the pillar; and

providing an impact ionization region of the pillar between the source region and the gate.

18. The method of claim 17, wherein doping the substrate with a P-type dopant comprises forming a source region exclusively within a silicon germanium material.

19. The method of claim 17, wherein forming a gate comprises depositing gate material over the pillar and removing at least a portion of the gate material from a surface of the pillar.

20. The method of claim 17, wherein doping the substrate with an N-type dopant to form a drain region comprises doping the substrate with phosphorous.

21. The method of claim 17, wherein etching the substrate to form a pillar comprises forming a pillar having a length of approximately 1,000 Å

.

22. A transistor comprising;

a gate;

an N-type drain region adjacent the gate;

a P-type source region separated from both the N-type drain region and the gate; and

an impact ionization region between the gate and the P-type source region.

23. The transistor of claim 22, wherein the impact ionization region comprises a germanium material.

24. The transistor of claim 22, wherein the gate comprises doped polysilicon material.

25. The transistor of claim 22, wherein the transistor exhibits a subthreshold slope less than 60 mV/decade.