ISOLATION STRUCTURE FOR SEMICONDUCTOR DEVICE WITH MULTIPLE TERMINALS

• US 20090236659A1
• Filed: 05/02/2007
• Published: 09/24/2009
• Est. Priority Date: 05/08/2006
• Status: Abandoned Application

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Kennedy, Ian, Parkin, James B., Gajda, Mark A., Brown, Adam R.
• Application Number:
  US12/299,917
• Publication Number:
  US 20090236659A1
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 21/765 by field effect H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell

Abstract

A semiconductor device has a first region (10) and a second region (20), gate trenches (50) being formed in paid first and second regions including insulated gates to control conduction between source regions (42) and a common drain region (40) through a body region separated into first (34) and second (36) body regions. Isolation between the first and second regions is provided in a simple way by providing a gap between the first and second body regions (34,36) formed by eg. at least one trench (52) or a part of the drain region.

Claims

1. A semiconductor device having opposed first and second major surfaces, comprising:

a body region of a first conductivity type adjacent to the first major surface wherein the body region is divided into a first body region forming part of a first transistor device in a first region and a second body region forming part of a second transistor device in a second region;

a drain region of second conductivity type opposite to the first conductivity type extending from the body region towards the second major surface;

a plurality of source regions of second conductivity type at the first major surface;

a plurality of gate trenches extending in the first body region and the second body region, the gate trenches including a plurality of insulated gates controlling conduction between the source regions through the body region into the drain region; and

an isolation region between the first and second body regions defined by at least one gap interrupting the body region between the first and second body regions to define the isolation region without additional edge termination in the source regions, drain region or body region between the first and second regions.

2. A semiconductor device according to claim 1 wherein the gate trenches extend continuously from the first body region through the isolation region into the second body region.

3. A semiconductor device according to claim 1, wherein the first transistor device is a main FET and the second transistor device is a sense FET.

4. A semiconductor device according to claim 1, wherein the isolation region comprises at least one trench extending along the boundary between first and second regions and extending from the first major surface through the body region to the drain region interrupting the body region to form the at least one gap.

5. A semiconductor device according to claim 4 including a plurality of trenches extending along the boundary between first and second regions with a pitch in the range of about 1 μ

m to 20 μ

m.

6. A semiconductor device according to claim 4, wherein there are at least eight trenches arranged side by side extending along the boundary between first and second regions.

7. A semiconductor device according to claim 1, wherein

the first and second body regions are separated by a part of the drain region extending to the first major surface to define the gap.

8. A semiconductor device according to claim 7 wherein the width of the isolation region is in the range of about 2.5 μ

m to 8 μ

m at the first major surface.

9. A semiconductor device according to claim 1, wherein isolation region is in the form of a closed loop at the first major surface enclosing the second body region and with the first body region outside the loop.

10. A semiconductor device according to claim 1, further comprising an insulated field plate extending over the first major surface over the isolation region.

11. Use of a semiconductor device according to claim 10 including applying a voltage to the insulated field plate.

12. A method of manufacturing a semiconductor device having first and second transistor regions, comprising:

forming a body region of a first conductivity type at the first major surface of a drain region of second conductivity type opposite to the first conductivity type, and defining the body region to have at least one gap interrupting the body region between the first and second regions to define an isolation region;

forming a plurality of source regions of second conductivity type at the first major surface in both the first and second transistor regions;

forming a plurality of gate trenches extending in the first body region and the second body region, and

filling the trenches with a plurality of insulated gates for controlling conduction between the source regions through the body region into the drain region;

wherein an isolation region between the first and second body regions is defined by the at least one gap interrupting the body region between the first and second body regions to define the isolation region without additional edge termination in the source regions, drain region or body region between the first and second regions.

13. A method according to claim 12 wherein the gate trenches are formed to extend continuously from the first body region through the isolation region into the second body region.

14. A method according to claim 12, wherein defining the body region to have at least one gap comprises forming a plurality of trenches extending along the boundary between first and second regions and extending from the first major surface through the body region to the drain region interrupting the body region to form the at least one gap.

15. A method according to claim 12, wherein defining the body region to have at least one gap consists of implanting the body region leaving a gap between a first body region in the first region and a second body region in the second region.