ELECTRONIC DEVICE AND MANUFACTURING THEREOF

• US 20090236749A1
• Filed: 03/18/2008
• Published: 09/24/2009
• Est. Priority Date: 03/18/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Schiess, Klaus, Mengel, Manfred, Otremba, Ralf, Ewe, Henrik
• Granted Patent: US 8,507,320 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/76155 Jetting means, e.g. ink jet
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/82039 using a laser
• CPC Class Codes: H01L 2224/82047 by mechanical means, e.g. severing, pressing, stamping
• CPC Class Codes: H01L 2224/82102 using jetting, e.g. ink jet
• CPC Class Codes: H01L 2224/92144 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/9222 Sequential connecting processes
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/25 : of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

One aspect is a method including providing a carrier having a first conducting layer, a first insulating layer over the first conducting layer, and at least one through-connection from a first face of the first insulating layer to a second face of the first insulating layer; attaching at least two semiconductor chips to the carrier; applying a second insulating layer over the carrier; opening the second insulating layer until the carrier is exposed; depositing a metal layer over the opened second insulating layer; and separating the at least two semiconductor chips after depositing the metal layer.

Claims

1. A method, comprising:

providing a carrier comprising a first conducting layer, a first insulating layer over the first conducting layer, and at least one through-connection from a first face of the first insulating layer to a second face of the first insulating layer;

attaching at least two semiconductor chips to the carrier;

applying a second insulating layer over the carrier;

opening the second insulating layer until the carrier is exposed;

depositing a metal layer over the opened second insulating layer; and

separating the at least two semiconductor chips after depositing the metal layer.

2. The method of claim 1, wherein the carrier further comprises a second conducting layer over the first insulating layer.

3. The method of claim 2, wherein at least one of the first conducting layer and the second conducting layer is a structured layer.

4. The method of claim 1, wherein the at least two semiconductor chips are attached to the carrier by soldering or adhesive bonding by means of a conducting adhesive.

5. The method of claim 1, wherein the second insulating layer is applied over the carrier by at least one of depositing an insulating material from a gas phase, depositing an insulating material from a solution, applying a mold material and laminating an insulating foil onto the carrier.

6. The method of claim 1, wherein the second insulating layer is opened by at least one of etching, electromagnetic radiation, laser ablation, stamping, drilling and sawing.

7. The method of claim 1, wherein the metal layer is deposited by at least one of electrochemically growing, sputtering, vacuum depositing, spray depositing and ink jet printing.

8. The method of claim 1, wherein the metal layer electrically couples at least one of the semiconductor chips to the carrier.

9. The method of claim 1, wherein the second insulating layer is covered with a mold material.

10. The method of claim 1, wherein each of the at least two semiconductor chips has a first electrode on a first surface and a second electrode on a second surface opposite to the first surface.

11. A device, comprising:

a carrier comprising a first conducting layer, a first insulating layer over the first conducting layer, and at least one first through-connection from a first face of the first insulating layer to a second face of the first insulating layer;

a semiconductor chip attached to the carrier;

a second insulating layer over the carrier and the semiconductor chip;

a metal layer over the second insulating layer;

a second through-connection through the second insulating layer electrically coupling the semiconductor chip to the metal layer; and

a third through-connection through the second insulating layer electrically coupling the carrier to the metal layer.

12. The device of claim 11, wherein the carrier further comprises a second conducting layer over the first insulating layer.

13. The device of claim 12, wherein the at least one first through-connection electrically couples the first conducting layer to the second conducting layer.

14. The device of claim 12, wherein the first conducting layer comprises a first contact pad, and the second conducting layer comprises a second contact pad.

15. The device of claim 14, wherein the shape of the first contact pad differs from the shape of the second contact pad.

16. The device of claim 14, wherein the surface area of the first contact pad is larger than the surface area of the second contact pad.

17. The device of claim 14, wherein the at least one first through-connection electrically couples the first contact pad to the second contact pad.

18. The device of claim 11, wherein the thickness of one of the metal layer and the second insulating layer is greater than the thickness of the semiconductor chip.

19. A device, comprising:

a carrier comprising a first insulating layer, a first contact pad attached to a first face of the first insulating layer, a second contact pad attached to a second face of the first insulating layer, and at least one first through-connection through the first insulating layer electrically coupling the first contact pad to the second contact pad, the shape of the first contact pad being different from the shape of the second contact pad; and

a semiconductor chip over to the carrier;

a second insulating layer over the carrier;

a metal layer over the second insulating layer and the semiconductor chip, the metal layer being electrically coupled to the semiconductor chip; and

a second through-connection through the second insulating layer electrically coupling the carrier to the metal layer.

20. The device of claim 19, wherein the carrier further comprises a third contact pad attached to the first face of the first insulating layer, a fourth contact pad attached to the second face of the first insulating layer, and a third through-connection through the first insulating layer electrically coupling the third contact pad to the fourth contact pad, wherein the second through-connection is arranged over the third through-connection and the shape of the third contact pad is different from the shape of the fourth contact pad.

21. The device of claim 19, wherein the surface area of the first contact pad is larger than the surface area of the second contact pad.

22. A method, comprising:

providing an insulating carrier;

attaching a semiconductor chip to the carrier;

applying an insulating layer over the carrier;

opening the insulating layer until the carrier is exposed;

depositing a metal layer over the opened insulating layer; and

forming at least one through-connection in the carrier after attaching the semiconductor chip to the carrier.

23. The method of claim 22, wherein the at least one through-connection is formed in the carrier after depositing the metal layer.

24. The method of claim 22, wherein the at least one through-connection is electrically connected to the semiconductor chip or the metal layer.

25. A device, comprising:

a carrier comprising a first conducting layer and a first insulating layer over the first conducting layer;

means in the first insulating layer for electrically coupling from a first face of the first insulating layer to a second face of the first insulating layer;

a semiconductor chip attached to the carrier;

a second insulating layer over the carrier and the semiconductor chip;

a metal layer over the second insulating layer; and

means in the second insulating layer for electrically coupling the semiconductor chip to the metal layer.