Circuit having an active clock shielding structure and semiconductor intergrated circuit including the same

• US 20090237107A1
• Filed: 03/12/2009
• Published: 09/24/2009
• Est. Priority Date: 03/18/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Bong-Hyun, Do, Kyung-Tae, Jeon, Jae-Han, Choi, Jung-Yun
• Granted Patent: US 8,013,628 B2
• Time in Patent Office: Days
• US Class Current: 326/21
• CPC Class Codes: H04B 15/02 Reducing interference from electric apparatus by means located at or near the interfering apparatus
• CPC Class Codes: H04B 2215/064 Reduction of clock or synthesizer reference frequency harmonics

Abstract

A circuit having an active clock shielding structure includes a logic circuit that receives a clock signal and performs a logic operation based on the clock signal, a power gating circuit that switches a mode of the logic circuit between an active mode and an sleep mode based on a power gating signal, a clock signal transmission line that transmits the clock signal to the logic circuit, and at least one power gating signal transmission line that transmits the power gating signal to the power gating circuit and functions as a shielding line pair with the clock signal transmission line.

Claims

1. A circuit having an active clock shielding structure, comprising:

a logic circuit configured to receive a clock signal and to perform a logic operation based on the clock signal;

a power gating circuit configured to switch a mode of the logic circuit between an active mode and a sleep mode based on a power gating signal;

a clock signal transmission line configured to transmit the clock signal to the logic circuit; and

at least one power gating signal transmission line configured to transmit the power gating signal to the power gating circuit, the at least one power gating signal transmission line functioning as a shielding line pair with the clock signal transmission line.

2. The circuit of claim 1, wherein the at least one power gating signal transmission line is configured to run in parallel with the clock signal transmission line.

3. The circuit of claim 2, wherein the at least one power gating signal transmission line encompasses the clock signal transmission line.

4. The circuit of claim 1, wherein the clock signal is transmitted during operation in the active mode and is not transmitted during operation in the sleep mode, and

wherein the operation mode of the logic circuit is changed from the active mode to the sleep mode based on an activation timing of the power gating signal, and the mode of the logic circuit is changed from the sleep mode to the active mode based on a deactivation timing of the power gating signal.

5. The circuit of claim 1, further comprising:

a retention flip-flop configured to receive a retention signal to preserve data during operation in the sleep mode based on the retention signal; and

at least one retention signal transmission line configured to transmit the retention signal to the retention flip-flop, the at least one retention signal transmission line functioning as a shielding line pair with the clock signal transmission line.

6. The circuit of claim 5, wherein the at least one power gating signal transmission line is configured to run in parallel with the clock signal transmission line.

7. The circuit of claim 6, wherein the at least one power gating signal transmission line encompasses the clock signal transmission line.

8. The circuit of claim 5, wherein the at least one retention signal transmission line is configured to run in parallel with the clock signal transmission line.

9. The circuit of claim 8, wherein the at least one retention signal transmission line encompasses the clock signal transmission line.

10. The circuit of claim 5, wherein both the at least one power gating signal transmission line and the at least one retention signal transmission line encompass the clock signal transmission line while running parallel with the clock signal transmission line.

11. The circuit of claim 5, wherein the clock signal is transmitted during operation in the active mode and is not transmitted during operation in the sleep mode, and

wherein the sleep mode includes a sleep-in mode, a sleep-state mode, and a sleep-out mode.

12. The circuit of claim 11, wherein the operation mode of the logic circuit is changed from the sleep-in mode to the sleep-state mode based on an activation timing of the power gating signal after the retention signal is activated during the sleep-in mode.

13. The circuit of claim 12, wherein the retention signal is deactivated during the sleep-out mode after the mode of the logic circuit is changed from the sleep-state mode to the sleep-out mode based on a deactivation timing of the power gating signal.

14. A semiconductor integrated circuit, comprising:

a clock signal gating unit configured to control a transmission of a clock signal;

a power gating control unit configured to control an activation of a power gating signal or a retention signal to determine a power gating operation; and

at least one circuit having an active clock shielding structure configured to receive the clock signal and to operate based on the power gating operation, the at least one circuit having the active clock shielding structure comprising;

a logic circuit configured to receive the clock signal and to perform a logic operation based on the clock signal;

a power gating circuit configured to switch a mode of the logic circuit between an active mode and a sleep mode based on the power gating signal;

a clock signal transmission line configured to transmit the clock signal to the logic circuit; and

at least one power gating signal transmission line configured to transmit the power gating signal to the power gating circuit, the at least one power gating signal transmission line functioning as a shielding line pair with the clock signal transmission line.

15. The semiconductor integrated circuit of claim 14, wherein the at least one power gating signal transmission line is configured to run in parallel with the clock signal transmission line.

16. The semiconductor integrated circuit of claim 15, wherein the at least one power gating signal transmission line encompasses the clock signal transmission line.

17. The semiconductor integrated circuit of claim 14, wherein the at least one circuit having the active clock shielding structure further comprises:

a retention flip-flop configured to receive a retention signal to preserve data during operation in the sleep mode based on the retention signal; and

at least one retention signal transmission line configured to transmit the retention signal to the retention flip-flop, the at least one retention signal transmission line functioning as a shielding line pair with the clock signal transmission line.

18. The semiconductor integrated circuit of claim 17, wherein the at least one power gating signal transmission line is configured to run in parallel with the clock signal transmission line.

19. The semiconductor integrated circuit of claim 18, wherein the at least one power gating signal transmission line encompasses the clock signal transmission line.

20. The semiconductor integrated circuit of claim 17, wherein the at least one retention signal transmission line is configured to run in parallel with the clock signal transmission line.

21. The semiconductor integrated circuit of claim 20, wherein the at least one retention signal transmission line encompasses the clock signal transmission line.

22. The semiconductor integrated circuit of claim 17, wherein both the at least one power gating signal transmission line and the at least one retention signal transmission line encompass the clock signal transmission line while running parallel with the clock signal transmission line.