ELECTRICAL PHYSICAL LAYER ACTIVITY DETECTOR
First Claim
1. A detector for detecting differential signal activity, the detector comprising:
- a differential input comprising a first input and a second input;
an output configured to provide an output signal of the detector, wherein the output signal is indicative of differential signal activity on the differential input; and
a buffer having an input coupled to the first input of the detector, and comprising output devices configured to provide an output of the buffer, wherein the output of the buffer is coupled to the second input of the detector;
wherein the output devices of the buffer are configured to half-wave rectify a differential input signal present at the differential input, to generate a half-wave rectified first signal; and
wherein the detector is configured to filter the half-wave rectified first signal to generate the output signal of the detector.
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Accused Products
Abstract
A low-current differential signal activity detector circuit may be configured to reject large common mode signals on differential input lines, while still detecting smaller differential signals applied to the same set of differential input lines. The detector circuit may comprise a translinear buffer that is driven at the buffer input and at the buffer output by the differential input signals. The differential signal thereby driving the inputs of the detector circuit may be half-wave rectified through the buffer output devices and may be filtered to provide the detected output. When applying a common mode signal, the buffer'"'"'s input and output may track each other, and no current may be rectified in the output devices, thus providing common-mode signal rejection. The detector circuit may also be configured with two buffers having their outputs coupled to a common node, each buffer input driven by a respective one of the differential input signals. The differential signal thereby driving the inputs of the detector circuit may be fully rectified through the output devices of the two buffers, and may be filtered to provide the detected output. The two buffers may be configured in a symmetrical structure that allows for the rejection of common-mode signals when the outputs of the buffers are coupled to a common node.
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Citations
25 Claims
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1. A detector for detecting differential signal activity, the detector comprising:
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a differential input comprising a first input and a second input; an output configured to provide an output signal of the detector, wherein the output signal is indicative of differential signal activity on the differential input; and a buffer having an input coupled to the first input of the detector, and comprising output devices configured to provide an output of the buffer, wherein the output of the buffer is coupled to the second input of the detector; wherein the output devices of the buffer are configured to half-wave rectify a differential input signal present at the differential input, to generate a half-wave rectified first signal; and wherein the detector is configured to filter the half-wave rectified first signal to generate the output signal of the detector. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for detecting differential signal activity, the method comprising:
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receiving a differential input signal; driving an input and an output of a buffer with the differential input signal; in response to said driving the input and the output of the buffer with the differential input signal, the output buffer half-wave rectifying the differential input signal, to generate a half-wave rectified signal; and filtering the half-wave rectified signal to provide an output proportional to a magnitude of the differential input signal to indicate differential signal activity. - View Dependent Claims (10, 11)
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12. A low-current circuit for detecting activity on a differential signal line, the low-current circuit comprising:
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first and second NMOS devices and first and second PMOS devices forming a translinear loop, wherein respective gate terminals of the first PMOS device and the second NMOS device are coupled to a first node to form an input of the translinear loop, and respective source terminals of the first NMOS device and the second PMOS device are coupled to a second node to form an output of the translinear loop; differential inputs configured to couple to the differential signal line, and comprising a first input coupled to the first node and a second input coupled to the second node; and an output configured at one of; a drain terminal of the second PMOS device;
ora drain terminal of the first NMOS device; wherein a DC voltage developed at the output is proportional to a size of a voltage difference between the first input of the low-current circuit and the second input of the low-current circuit. - View Dependent Claims (13, 14, 15, 16)
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17. A detector circuit having differential inputs and an output, the detector circuit comprising:
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a first, second, third, and fourth transistor, each transistor having a respective control terminal and respective first and second channel terminals; wherein the respective control terminals of the first and second transistor are coupled to a first node, the respective first channel terminals of the third and fourth transistors are coupled to a second node, the first channel terminal of the first transistor is coupled to the control terminal of the third transistor, and the first channel terminal of the second transistor is coupled to the control terminal of the fourth transistor; wherein a first input of the differential inputs is coupled to the first node, and a second input of the differential inputs is coupled to the second node; wherein the output of the detector circuit is provided at one of; a second channel terminal of the fourth transistor;
ora second channel terminal of the third transistor; wherein a DC voltage developed at the output of the detector circuit in response to a differential input signal applied at the differential inputs is proportional to a size of a voltage difference between the first input and the second input. - View Dependent Claims (18, 19)
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20. A detection circuit comprising:
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a differential input comprising a first input and a second input; an output configured to provide a first output signal of the detection circuit, wherein the first output signal is indicative of differential signal activity on the differential input; a first buffer having an input coupled to the first input of the detection circuit, and comprising an output stage configured to provide an output of the first buffer; and a second buffer having an input coupled to the second input of the detection circuit, and comprising an output stage configured to provide an output of the second buffer; and a load circuit; wherein the output of the first buffer and the output of the second buffer are coupled to a first node; wherein the output stage of the first buffer and the output stage of the second buffer are configured to fully rectify a differential input signal present at the differential input, to generate a fully rectified first signal; and wherein the load circuit is configured to filter the fully rectified first signal to generate the first output signal of the detector. - View Dependent Claims (21, 22, 23, 24, 25)
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Specification