RFID TAGS WITH POWER RECTIFIERS THAT HAVE BIAS

• US 20090237220A1
• Filed: 06/01/2009
• Published: 09/24/2009
• Est. Priority Date: 09/26/2005
• Status: Active Grant

• Current Assignee: Impinj, Inc.
• Original Assignee: Impinj, Inc.
• Inventors: Oliver, Ronald A., Diorio, Christopher J.
• Granted Patent: US 8,244,201 B2
• Time in Patent Office: Days
• US Class Current: 340/10.340
• CPC Class Codes: G06K 19/0701 at least one of the integrated circuit chips comprising an arrangement for power management
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs

Abstract

A system and method for generating a rectified signal in a RFID tag. An alternating signal is received by the RFID tag, and a first phase of the alternating signal is coupled to a gate and to a first non-controlling terminal of a first switching transistor. The non-controlling terminal of the first switching transistor is one of a source and a drain of the first switching transistor. A first bias voltage is applied between the first non-controlling terminal and the gate of the first switching transistor and a rectified voltage is received between the first non-controlling terminal and a second non-controlling terminal of the first switching transistor.

Claims

1. A method for generating a rectified signal in a RFID tag, the method comprising:

receiving an alternating signal;

coupling a first phase of the alternating signal to a gate and to a first non-controlling terminal of a first switching transistor, the first non-controlling terminal of the first switching transistor being one of a source and a drain of the first switching transistor;

applying a first bias voltage between the first non-controlling terminal and the gate of the first switching transistor; and

receiving a rectified voltage between the first non-controlling terminal and a second non-controlling terminal of the first switching transistor.

2. The method of claim 1, wherein the first phase is coupled to the gate and to the first non-controlling terminal of the first switching transistor via a single capacitor.

3. The method of claim 1, wherein the first phase is coupled to the gate of the first switching transistor via a first capacitor, and the first phase is coupled to the first non-controlling terminal via a second capacitor.

4. The method of claim 1, further comprising adjusting the bias voltage.

5. The method of claim 1, wherein the first bias voltage is applied by applying a bias current to a reference transistor having one terminal that is coupled to the gate of the first switching transistor.

6. The method of claim 5, wherein the reference transistor is coupled to form a floating gate with the gate of the first switching transistor.

7. The method of claim 5, wherein the reference transistor is coupled to the gate of the first switching transistor as a current mirror.

8. The method of claim 5, further comprising adjusting the bias current.

9. The method of claim 5, wherein the reference transistor is coupled to the gate of the first switching transistor as a switched capacitor.

10. The method of claim 8, wherein adjusting the bias current is based on an amplitude of the alternating signal coupled to the gate of the first switching transistor.

11. The method of claim 8, wherein adjusting the bias current is based on a voltage across the first and second non-controlling terminals of the first switching transistor.

12. The method of claim 8, wherein adjusting the bias current is based on a current through the first switching transistor.

13. The method of claim 8, wherein adjusting the bias current is based on the rectified voltage.

14. The method of claim 8, wherein adjusting the bias current is based on a current of a rectified output signal received from a non-controlling terminal of one of the first and second switching transistors.

15. The method of claim 1, further comprising:

coupling a second phase of the alternating signal to a gate and to a first non-controlling terminal of a second switching transistor, the first non-controlling terminal of the second switching transistor being one of a source and a drain of the second switching transistor; and

applying a second bias voltage between the first non-controlling terminal and the gate of the second switching transistor, wherein the first non-controlling terminal of the second switching transistor is coupled to the second non-controlling terminal of the first switching transistor, and wherein the rectified voltage is received between the first non-controlling terminal of the first switching transistor and a second non-controlling terminal of the second switching transistor.

16. The method of claim 1, further comprising:

coupling a second phase of the alternating signal to a first non-controlling terminal of a second switching transistor, the first non-controlling terminal of the second switching transistor being one of a source and a drain of the second switching transistor; and

applying a second bias voltage between the second non-controlling terminal and a gate of the second switching transistor, wherein the first non-controlling terminal of the second switching transistor is coupled to the second non-controlling terminal of the first switching transistor, and wherein the rectified voltage is received between the first non-controlling terminal of the first switching transistor and a second non-controlling terminal of the second switching transistor.

17. The method of claim 16, wherein the first switching transistor is an n-channel field effect transistor and the second switching transistor is a p-channel field effect transistor, and the method further comprises applying a second bias voltage between a coupling capacitor and the gate of the second switching transistor.

18. The method of claim 17, wherein the bias voltage is applied by applying a first bias current to a first reference transistor coupled to the gate of the n-channel field effect transistor and applying a second bias current to a second reference transistor coupled to the gate of the p-channel field effect transistor.

19. The method of claim 18, further comprising adjusting the first and second bias currents.

20. The method of claim 18, wherein the first and second currents are the same current.

21. An RFID circuit comprising:

a means for receiving an alternating signal;

a means for coupling a first phase of the alternating signal to a gate and to a first non-controlling terminal of a first switching transistor, the first non-controlling terminal of the first switching transistor being one of a source and a drain of the first switching transistor;

a means for applying a first bias voltage between the first non-controlling terminal and the gate of the first switching transistor; and

a means for receiving a rectified voltage between the first non-controlling terminal and a second non-controlling terminal of the first switching transistor.

22. The RFID circuit of claim 21, wherein the first phase is coupled to the gate and to the first non-controlling terminal of the first switching transistor via a single capacitor.

23. The RFID circuit of claim 21, wherein the first phase is coupled to the gate of the first switching transistor via a first capacitor, and the first phase is coupled to the first non-controlling terminal via a second capacitor.

24. The RFID circuit of claim 21, further comprising a means for adjusting the bias voltage.

25. The RFID circuit of claim 21, further comprising:

a means for coupling a second phase of the alternating signal to a gate and to a first non-controlling terminal of a second switching transistor, the first non-controlling terminal of the second switching transistor being one of a source and a drain of the second switching transistor; and

a means for applying a second bias voltage between the first non-controlling terminal and the gate of the second switching transistor, wherein the first non-controlling terminal of the second switching transistor is coupled to the second non-controlling terminal of the first switching transistor, and wherein the rectified voltage is received between the first non-controlling terminal of the first switching transistor and a second non-controlling terminal of the second switching transistor.

26. The RFID circuit of claim 21, further comprising:

a means for coupling a second phase of the alternating signal to a first non-controlling terminal of a second switching transistor, the first non-controlling terminal of the second switching transistor being one of a source and a drain of the second switching transistor; and

a means applying a second bias voltage between the second non-controlling terminal and a gate of the second switching transistor, wherein the first non-controlling terminal of the second switching transistor is coupled to the second non-controlling terminal of the first switching transistor, and wherein the rectified voltage is received between the first non-controlling terminal of the first switching transistor and a second non-controlling terminal of the second switching transistor.

27. The RFID circuit of claim 26 wherein the first switching transistor is an n-channel field effect transistor and the second switching transistor is a p-channel field effect transistor, and the method further comprises applying a second bias voltage between a coupling capacitor and the gate of the second switching transistor.

28. The RFID circuit of claim 27 wherein the bias voltage is applied by applying a first bias current to a first reference transistor coupled to the gate of the n-channel field effect transistor and applying a second bias current to a second reference transistor coupled to the gate of the p-channel field effect transistor.

29. The RFID circuit of claim 28, further comprising a means for adjusting the first and second bias currents.