PROCESS VARIATION COMPENSATED MULTI-CHIP MEMORY PACKAGE

• US 20090237970A1
• Filed: 11/04/2008
• Published: 09/24/2009
• Est. Priority Date: 03/19/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: CHUNG, Hoe-Ju
• Granted Patent: US 8,054,663 B2
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

A multi-chip package memory includes an interface chip generating at least one reference signal defined in relation to a reference process variation, and a stacked plurality of memory chips electrically connected to the interface chip via a vertical connection path and receiving the reference clock signal via the vertical connection path, wherein each one of the stacked plurality of memory chips is characterized by a process variation and actively compensates for said process variation in relation to the reference signal.

Claims

1. A multi-chip package memory comprising:

an interface chip generating clock signal and a reference delayed clock signal in relation to a defined reference process variation; and

a stacked plurality of memory chips electrically connected to the interface chip via a vertical connection path and receiving the clock signal and the reference delayed clock signal via the vertical connection path,

wherein each one of the stacked plurality of memory chips is characterized by a process variation and compensates for said process variation in relation to the reference delayed clock signal.

2. The multi-chip package memory of claim 1, wherein each one of the stacked plurality of memory chips generates an internal power voltage in relation to the clock signal and the reference delayed clock signal.

3. The multi-chip package memory of claim 2, wherein

the interface chip is transfer memory chip having a process variation equal to the reference process variation.

4. The multi-chip package memory of claim 3, wherein each one of the stacked plurality of memory chips comprises:

a delay unit receiving the clock signal and the internal power voltage, and generating a corresponding delayed clock signal;

a phase detection unit comparing a phase of the reference delayed clock signal with a phase of the delayed clock signal and generating a phase difference signal; and

a power voltage control unit controlling the internal power voltage in response to phase difference signal.

5. The multi-chip package memory of claim 4, wherein the power voltage control unit comprises:

a control unit generating a control signal in response to the phase difference signal; and

a transistor giving a gate receiving the control signal, a first side connected to an external power voltage, and a second side connected to the delay unit.

6. The multi-chip package memory of claim 4, wherein each one of the stacked plurality of memory chips further comprises:

a first buffer receiving the clock signal and providing a buffered clock signal to the delay unit; and

a second buffer receiving the reference delayed clock signal and providing a buffered reference delayed clock signal to the phase detection unit,

wherein the first buffer and the second buffer have a similar delay characteristic.

7. The multi-chip package memory of claim 3, wherein the transfer memory chip comprises a reference delay unit receiving the clock signal and generating the reference delayed clock signal.

8. The multi-chip package memory of claim 7, wherein the reference delay unit imparts a greater delay to the clock signal as the operating frequency of the multi-chip package memory is relatively lower.

16. The multi-chip package memory of claim 1, wherein the vertical connection path is implemented using at least one through silicon via (TSV) and traverses the multi-chip package memory from an upper surface of the interface chip to an uppermost memory chip in the stacked plurality of memory chips.

17. The multi-chip package memory of claim 1, further comprising:

a printed circuit board (PCB) mounting the interface chip and the stacked plurality of memory chips.

18. The multi-chip package memory of claim 1, wherein the interface chip controls compensation for process variations associated with respective ones of the stacked plurality of memory chips during an initialization process performed by the multi-chip package memory.

19. The multi-chip package memory of claim 1, wherein the interface chip controls compensation for process variations associated with respective ones of the stacked plurality of memory chips during periodic compensation processes performed during operation of the multi-chip package memory.

20. The multi-chip package memory of claim 19, wherein the periodic compensation processes are each associated with a refresh process applied to at least one of the stacked plurality of memory chips.

9. A multi-chip package memory comprising:

an interface chip providing a reference signal in relation to a defined reference process variation; and

a stacked plurality of memory chips electrically connected to the interface chip via a vertical connection path and receiving the reference signal via the vertical connection path,

wherein each one of the stacked plurality of memory chips is characterized by a process variation and compensates for said process variation in relation to the reference signal and comprises;

a current source having a first side connected to an external power voltage source and providing a current;

a resistance device connected to and interposed between ground voltage and the second side the current source;

a comparison device comparing a voltage provided by the resistance device with the reference signal; and

a control unit controlling the current source in response to an output signal provided by the comparison device.

10. The multi-chip package memory of claim 9, wherein the resistance device comprises a PMOS transistor having a gate and a first side connected to ground voltage and a second side connected to the current source.

11. The multi-chip package memory of claim 9, wherein the resistance device comprises an NMOS transistor having a gate and a first side connected to current source and a second side connected to ground voltage.

12. The multi-chip package memory of claim 9, wherein the interface chip is a transfer memory chip having a process variation equal to the reference process variation and comprising:

a reference current source having one side connected to an external power voltage source and providing a current; and

a reference resistance device connected to and interposed between ground voltage and a second side of the reference current source, wherein the reference signal is a voltage provided by the reference resistance device.

13. The multi-chip package memory of claim 12, wherein the reference resistance device comprises a PMOS transistor having a gate and a first side connected to ground voltage, and a second end connected to the reference current source.

14. The multi-chip package memory of claim 12, wherein the reference resistance device comprises an NMOS transistor having a gate and a first side connected to the reference current source and a second side connected to ground voltage.

15. The multi-chip package memory of claim 9, wherein the reference signal is a voltage that varies in level in an inverse relationship with an operating frequency of the multi-chip package memory.