SEMICONDUCTOR MEMORY DEVICES WITH INTERFACE CHIPS HAVING MEMORY CHIPS STACKED THEREON

• US 20090237971A1
• Filed: 02/06/2009
• Published: 09/24/2009
• Est. Priority Date: 03/19/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Chung, Hoe-ju, Lee, Jung-bae
• Granted Patent: US 8,102,688 B2
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

A semiconductor memory device includes a controller, a plurality of substrates, and a plurality of stacked memories that are spaced apart and sequence on each of the substrates. Each of the stacked memories includes an interface chip that is connected to the respective substrate and a plurality of memory chips that are stacked on the interface chip. The controller is configured to control the stacked memories. The interface chips are configured to forward a command signal from the controller through each interface chip in the sequence of stacked memories that is intervening between the controller and a selected stacked memory to which the command signal is directed. The interface chips may forward the command signal from one end of the sequence of the stacked memories on one of the substrates to the selected stacked memory, and forward a response signal from the selected stacked memory through the remaining stacked memories in the sequence on the substrate back to the controller or through the same sequence of stacked memories that was taken by the command signal.

Claims

1. A semiconductor memory device comprising:

first through mth substrates, wherein m is a natural number greater than 1; and

first through nth stacked memories spaced apart and connected to each of the first through mth substrates, each of the first through nth stacked memories including an interface chip that is connected the respective substrate and further including a plurality of memory chips stacked on the interface chip, wherein n is a natural number,

wherein a kth one of the interface chips transmits a signal to a k+1th interface chip connected to the same substrate, wherein k is a natural number that is equal to or greater than 1 and is less than or equal to n−

1.

2. The semiconductor memory device of claim 1, further comprising a controller that is configured to control the first through nth stacked memories connected to each of the first through mth substrates,

wherein the controller transmits a command signal, which is directed to the nth interface chip connected to the first substrate, to the first one of the interface chips connected to the first substrate and which relays the command signal to the nth interface chip connected to the first substrate, and the controller receives a response signal from the nth interface chip connected to the first substrate.

3. The semiconductor memory device of claim 2, wherein:

the kth interface chip forwards the command signal to the k+1th interface chip using a first signaling mode;

the controller transmits the command signal to the first interface chip and receives the response signal from the nth interface chip using a second signaling mode that is different than the first signaling mode, and

the controller and stacked memories are configured so that power consumption in the first signaling mode is less than in the second signaling mode.

4. The semiconductor memory device of claim 3, wherein the controller transmits and receives signals using the second signaling mode by transmitting a pair of differential signals to the first interface chip and receiving a pair of differential signals from the nth interface chip.

5. The semiconductor memory device of claim 2, wherein the kth interface chip is connected to the k+1th interface chip in a fly-by configuration or a daisy chain configuration.

6. The semiconductor memory device of claim 1, further comprising a controller that is configured to control the first through nth stacked memories connected to each of the first through mth substrates, wherein:

the controller transmits a command signal, which is directed to the first interface chip connected to an a+1th substrate, through the first interface chip connected to an ath substrate, wherein a is a natural number equal to or greater than 1 and less than or equal to m−

1;

the first interface chip connected to the ath substrate responds to the command signal by transmitting the command signal to the first interface chip connected to the a+1th substrate; and

the nth interface chip connected to the ath substrate receives a response signal from the nth interface chip connected to the a+1th substrate.

7. The semiconductor memory device of claim 6, wherein:

the first interface chip connected to the ath substrate transmits the command signal to the first interface chip connected to the a+1th substrate using a first signaling mode;

the nth interface chip connected to the ath substrate receives the response signal from the nth interface chip connected to the a+1th substrate using the first signaling mode;

the controller transmits the command signal to the first interface chip connected to the a+1th substrate and receives the response signal from the nth interface chip connected to the a+1th substrate using a second signaling mode that is different than the first signaling mode; and

the controller and the stacked memories are configured so that power consumption in the first signaling mode is less than or equal to power consumption in the second signaling mode.

8. The semiconductor memory device of claim 6, wherein:

wherein the controller transmits and receives signals using the second signaling mode by transmitting a pair of differential signals to the first interface chip connected to the ath substrate and receiving a pair of differential signals from the nth interface chip connected to the a+1th substrate;

the first interface chip connected to the ath substrate responds to the pair of differential signals by transmitting according to the first signaling mode using a pair of differential signals or a single signal to the first interface chip connected to the a+1th substrate; and

the nth interface chip connected to the ath substrate receives according to the first signaling mode a pair of differential signals or a single signal from the nth interface chip connected to the a+1th substrate.

9. A semiconductor memory device comprising:

first through mth substrates, wherein m is a natural number greater than 1; and

first through nth stacked memories spaced apart and connected to each of the first through mth substrates, each of the first through nth stacked memories including an interface chip that is connected to the respective substrate and further including a plurality of memory chips stacked on the interface chip, wherein n is a natural number,

wherein a kth one of the interface chips exchanges a signal with a k+1th interface chip connected to the same substrate, wherein k is a natural number that is equal to or greater than 1 and is less than or equal to n−

1.

10. The semiconductor memory device of claim 9, further comprising a controller that is configured to control the first through nth stacked memories connected to each of the first through mth substrates,

wherein the controller exchanges signals with the first interface chip connected to the first substrate to read data from one of the stacked memories on one of the substrates other than the first substrate.

11. The semiconductor memory device of claim 10, wherein:

the kth interface chip exchanges a signal with the k+1th interface chip using a first signaling mode;

the controller exchanges a signal with the first interface chip using a second signaling mode that is different than the first signaling mode; and

the controller and stacked memories are configured so that power consumption in the first signaling mode is less than in the second signaling mode.

12. The semiconductor memory device of claim 10, wherein the controller transmits and receives signals using the second signaling mode by transmitting a pair of differential signals to the first interface chip and receiving a pair of differential signals from the nth interface chip.

13. The semiconductor memory device of claim 9, further comprising a controller that is configured to control the first through nth stacked memories connected to each of the first through mth substrates, wherein:

the controller transmits a command signal, which is directed to the first interface chip connected to an a+1th substrate, through the nth interface chip connected to an ath substrate, wherein a is a natural number equal to or greater than 1 and less than or equal to m−

1;

the nth interface chip connected to the ath substrate responds to the command signal by transmitting the command signal to the first interface chip connected to the a+1th substrate; and

the nth interface chip connected to the ath substrate receives a response signal from the first interface chip connected to the a+1th substrate.

14. The semiconductor memory device of claim 13, wherein:

the nth interface chip connected to the ath substrate exchanges a signal with the first interface chip connected to the a+1th substrate using a first signaling mode;

the controller exchanges a signal with the first interface chip using a second signaling mode that is different than the first signaling mode; and

the controller and the stacked memories are configured so that power consumption in the first signaling mode is less than or equal to power consumption in the second signaling mode.

15. The semiconductor memory device of claim 13, wherein:

the controller exchanges a pair of differential signals with the first interface chip using the second signaling mode; and

the nth interface chip connected to the ath substrate exchanges a pair of differential signals or a single signal with the first interface chip connected to the a+1th substrate using the first signaling mode.

16. The semiconductor memory device of claim 9, further comprising a controller that is configured to control the first through nth stacked memories connected to each of the first through mth substrates,

wherein the controller exchanges a signal with an ith interface chip connected to the first substrate, and wherein i is a natural number equal to or greater than 2 and less than or equal to n−

1.

17. The semiconductor memory device of claim 16, wherein:

the kth interface chip exchanges a signal with the k+1th interface chip using a first signaling mode;

the controller exchanges a signal with the ith interface chip using a second signaling mode that is different than the first signaling mode; and

the controller and the stacked memories are configured so that power consumption in the first signaling mode is less than in the second signaling mode.

18. The semiconductor memory device of claim 16, wherein the ith interface chip connected to an ath substrate exchanges a signal with the ith interface chip connected to an a+1th substrate, wherein a is a natural number equal to or greater than 1 and less than or equal to m−

1.

19. The semiconductor memory device of claim 18, wherein:

the ith interface chip connected to the ath substrate exchanges a signal with the ith interface chip connected to the a+1th substrate using a first signaling mode;

the controller exchanges a signal with the ith interface chip using a second signaling mode that is different than the first signaling mode; and

the controller and the stacked memories are configured so that power consumption in the first signaling mode is less than or equal to power consumption in the second signaling mode.