N-ary Three-Dimensional Mask-Programmable Read-Only Memory

• US 20090237976A1
• Filed: 06/04/2009
• Published: 09/24/2009
• Est. Priority Date: 07/15/2005
• Status: Active Grant

• Current Assignee: Guobiao Zhang
• Original Assignee: Guobiao Zhang
• Inventors: ZHANG, Guobiao
• Granted Patent: US 7,821,080 B2
• Time in Patent Office: Days
• US Class Current: 365/105
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/50 having transistors on different levels, e.g. 3D ROM

Abstract

N-ary three-dimensional mask-programmable read-only memory (N-3DMPROM) stores multi-bit-per-cell. Its memory cells can have N states (N>2) and data are stored as N-ary codes. N-3DMPROM has a larger storage density than the prior-art binary 3D-MPROM. One advantage of N-3DROM over other N-ary memory (e.g. multi-level-cell flash) is that its array efficiency can be kept high. N-3DMPROM could be geometry-defined, junction-defined, or a combination thereof.

Claims

1. An N-ary three-dimensional mask-programmable read-only memory (N-3DMPROM), comprising:

a semiconductor substrate including transistors;

a plurality of vertically stacked mask-programmable memory levels, said memory levels stacked above and coupled to said substrate, each of said memory level comprising a plurality of address-selection lines and mask-programmable memory cells, each of said memory cells comprising a diode-like device and having one of at least N possible states with N>

2, wherein memory cells in different states have different ranges of read current at a read voltage;

wherein said substrate further comprises means for converting data from said memory levels into binary.

2. The N-ary three-dimensional mask-programmable read-only memory according to claim 1, wherein at least a portion of said converting means is located directly under said memory levels.

3. The N-ary three-dimensional mask-programmable read-only memory according to claim 1, wherein memory cells in a same state have substantially the same geometry, and memory cells in at least three different states have different geometries.

4. The N-ary three-dimensional mask-programmable read-only memory according to claim 1, wherein memory cells in a same state have substantially the same junction, and memory cells in at least two different states have different junctions.

5. The N-ary three-dimensional mask-programmable read-only memory according to claim 1, wherein said memory levels further comprise a plurality of dummy cells, each of said dummy cells comprising a diode-like device;

and said substrate further comprises means for comparing a first input from a selected memory cell and a second input from a selected dummy cell.

6. The N-ary three-dimensional mask-programmable read-only memory according to claim 4, wherein said second input is coupled to first and second dummy cells, said first dummy cell having a first one of said N possible states and said second dummy cell having a second one of said N possible states.

7. The N-ary three-dimensional mask-programmable read-only memory according to claim 1, wherein N is a non-integral power of 2.

8. An N-ary three-dimensional mask-programmable read-only memory (N-3DMPROM), comprising:

a semiconductor substrate including transistors;

a plurality of vertically stacked mask-programmable memory levels, said memory levels stacked above and coupled to said substrate, each of said memory level comprising a plurality of address-selection lines and mask-programmable memory cells, each of said memory cells comprising a diode-like device and having one of at least N possible states with N>

2, wherein memory cells in a same state have substantially the same geometry, and memory cells in at least three different states have different geometries and have different ranges of read current at a read voltage;

wherein said substrate further comprises means for converting data from said memory levels into binary.

9. The N-ary three-dimensional mask-programmable read-only memory according to claim 8, wherein said diode-like device comprises a partial-diode between an upper address-selection line and a lower address-selection line, and memory cells in at least two different states have different partial-diodes.

10. The N-ary three-dimensional mask-programmable read-only memory according to claim 9, wherein an edge of said partial-diode aligns with an edge of said upper address-selection line.

11. The N-ary three-dimensional mask-programmable read-only memory according to claim 10, wherein an edge of said partial-diode aligns with an inside edge of an address-selection-line pair.

12. The N-ary three-dimensional mask-programmable read-only memory according to claim 8, wherein the diode-areas of partial diodes from different states are unevenly distributed.

13. The N-ary three-dimensional mask-programmable read-only memory according to claim 8, wherein N is a non-integral power of 2.

14. The N-ary three-dimensional mask-programmable read-only memory according to claim 8, wherein memory cells in at least two different states have different junctions.

15. An N-ary three-dimensional mask-programmable read-only memory (N-3DMPROM), comprising:

a semiconductor substrate including transistors;

a plurality of vertically stacked mask-programmable memory levels, said memory levels stacked above and coupled to said substrate, each of said memory level comprising a plurality of address-selection lines and mask-programmable memory cells, each of said memory cells comprising a diode-like device and having one of at least N possible states with N>

2, wherein memory cells in a same state have substantially the same junction, and memory cells in at least two different states have different junctions and have different ranges of read current at a read voltage;

wherein said substrate further comprises means for converting data from said memory levels into binary.

16. The N-ary three-dimensional mask-programmable read-only memory according to claim 15, wherein said diode-like device has a doping profile, and memory cells in at least two different states have different doping profiles.

17. The N-ary three-dimensional mask-programmable read-only memory according to claim 15, further comprising means for limiting the read current through the memory cell under read.

18. The N-ary three-dimensional mask-programmable read-only memory according to claim 15, wherein at least two read voltages are applied in sequence to the selected memory cell during read.

19. The N-ary three-dimensional mask-programmable read-only memory according to claim 15, wherein N is a non-integral power of 2.

20. The N-ary three-dimensional mask-programmable read-only memory according to claim 15, wherein memory cells in at least three different states have different geometries.